MCIMX503CVM8B datasheet(71/134 Pages) FREESCALE

部件名	MCIMX503CVM8B

功能描述	i.MX50 Applications Processors for Consumer Products

PDF	134 Pages

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制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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Electrical Characteristics

i.MX50 Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

NOTE

The DDR15,16 could be adjusted by the parameter “DLL_WR_DELAY”;

The ideal case is that SDQS is center aligned to the DRAM_D data valid

window;

For this table, HW_DRAM_PHY15[14:8] (DLL_WR_DELAY) = 0x10;

4.8.4

DRAM Data Input Timing

DRAM Data input timing is defined for all DDR types: DDR2, LPDDR1, and LPDDR2.

DDR16

CK >= 200 MHz

DQ & DQM output hold time relative to DQS

tDH

0.5 tCK

- 1.3

—ns

DDR15

CK < 200 MHz

DQ & DQM output setup time relative to DQS

tDS

—

DDR16

CK < 200 MHz

DQ & DQM output hold time relative to DQS

tDH

—

Table 47. DDR2 Input AC Timing

Description

Symbol

Min

Max

Unit

DDR20

Positive DQS latching edge to associated CK edge

tDQSCK

-0.5 tCK

—

Table 46. DDR Output AC Timing

Description

Symbol

Min

Max

Unit

Figure 31. DRAM Data Input Timing

DRAM_SDCLK

DRAM_SDCLK_B

DRAM_SDQS

DDR21

DDR22

DDR20

DRAM_D

DRAM_SDQS_B

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