MCIMX503CVM8B datasheet(15/134 Pages) FREESCALE

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Modules List

i.MX50 Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

SDMA

Smart Direct

Memory

Access

Master

Connectivity

Peripherals

The SDMA is multi-channel flexible DMA engine. It helps in maximizing

system performance by offloading various cores in dynamic data routing.

The SDMA features list is as follows:

• Powered by a 16-bit instruction-set micro-RISC engine

• Multi-channel DMA supports up to 32 time-division multiplexed DMA

channels

• 48 events with total flexibility to trigger any combination of channels

• Memory accesses including linear, FIFO, and 2D addressing

• Shared peripherals between ARM Cortex-A8 and SDMA

• Very fast context-switching with two-level priority-based preemptive

multi-tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers (increment, decrement,

and no address changes on source and destination address)

• DMA ports can handle uni-directional and bi-directional flows (copy mode)

• Up to 8-word buffer for configurable burst transfers for EMI

• Support of byte-swapping and CRC calculations

• A library of scripts and API is available

SJC

Secure JTAG

Controller

System

Control

Peripherals

The Secure JTAG Controller provides a mechanism for regulating JTAG

access, preventing unauthorized JTAG usage while allowing JTAG access for

manufacturing tests and software debugging.

The i.MX50 JTAG port provides debug access to several hardware blocks

including the ARM processor and the system bus, therefore, it must be

accessible for initial laboratory bring-up, manufacturing tests and

troubleshooting, and for software debugging by authorized entities. However,

if the JTAG port is left unsecured it provides a method for executing

unauthorized program code, getting control over secure applications, and

running code in privileged modes.

The Secure JTAG controller provides three different security modes that can

be selected through an e-fuse configuration to prevent unauthorized JTAG

access.

SPBA

Shared

Peripheral Bus

Arbiter

System

Control

Peripherals

SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP

bus) arbiter.

SRTC

Secure Real

Time Clock

Security

Peripherals

The SRTC incorporates a special System State Retention Register (SSRR)

that stores system parameters during system shutdown modes. This register

and all SRTC counters are powered by dedicated supply rail NVCC_SRTC.

The NVCC_SRTC can be energized separately even if all other supply rails

are shut down. This register is helpful for storing warm boot parameters. The

SSRR also stores the system security state. In case of a security violation,

the SSRR marks the event (security violation indication).

Table 4. i.MX50 Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

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