MCIMX503CVM8B datasheet(80/134 Pages) FREESCALE

80 / 134 page

i.MX50 Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Electrical Characteristics

Figure 39. RMII Serial Management Channel Timing Diagram

4.9.4.3

RMII Mode Timing

In RMII mode, FEC_TX_CLK is used as the REF_CLK which is a 50 MHz ± 50 ppm continuous

reference clock. FEC_RX_DV is used as the CRS_DV in RMII, and other signals under RMII mode

include FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and optional FEC_RX_ER.

The RMII mode timings are shown in Table 57 and Figure 40.

M14

FEC_MDC pulse width high

40% 60% FEC_MDC period

M15

FEC_MDC pulse width low

40% 60% FEC_MDC period

Table 57. RMII Signal Timing

No.

Characteristics

Min

Max

Unit

M16

REF_CLK(FEC_TX_CLK) pulse width high

35%

65%

REF_CLK period

M17

REF_CLK(FEC_TX_CLK) pulse width low

35%

65%

REF_CLK period

M18

REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid

—

M19

REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid

—

M20

FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to

REF_CLK setup

4—

M21

REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER hold

—

Table 56. RMII Transmit Signal Timing (continued)

Characteristics

Min

Max

Unit

FEC_MDC (output)

FEC_MDIO (output)

M14

M15

M10

M11

M12

M13

FEC_MDIO (input)

MCIMX503CVM8B 数据表(PDF) 80 Page - Freescale Semiconductor, Inc

MCIMX503CVM8B 数据表(HTML) 80 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载