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MCIMX503CVM8B 数据表(PDF) 14 Page - Freescale Semiconductor, Inc |
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MCIMX503CVM8B 数据表(HTML) 14 Page - Freescale Semiconductor, Inc |
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14 / 134 page  i.MX50 Applications Processors for Consumer Products, Rev. 2 14 Freescale Semiconductor Modules List GPU2Dv1 Graphics Processing Unit-2D, ver. 1 Display Peripherals The GPU2Dv1 provides hardware acceleration for 2D graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD1080 resolution. I2C-1 I2C-2 I2C-3 I2C Interface Connectivity Peripherals I2C provides serial interface for controlling peripheral devices. Data rates of up to 400 kbps are supported. OCOTP Controller On-chip OTP controller Security Peripherals The on-chip one-time -programmable (OCOTP) ROM serves the functions of hardware and software capability bits, Freescale operations and unique-ID, the customer-programmable cryptography key, and storage of various ROM and general purpose configuration bits. IOMUXC IOMUX Control Slave Connectivity Peripherals This module enables flexible I/O multiplexing. Each I/O pad has default as well as several alternate functions. The alternate functions are software configurable. KPP Keypad Port Slave Connectivity Peripherals The KPP supports an 8 × 8 external keypad matrix. The KPP features are as follows: • Open drain design • Glitch suppression circuit design • Multiple keys detection • Standby key press detection OWIRE One-Wire Interface Slave Connectivity Peripherals One-Wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example, Dallas DS2502. PWM-1 PWM-2 Pulse Width Modulation Slave Connectivity Peripherals The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound. RAM 128 Kbytes Internal RAM Internal Memory The On-Chip Memory controller (OCRAM) module, is an interface between the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is used for controlling the 128 Kbyte multimedia RAM, through a 64-bit AXI bus. ROM 96 Kbytes Boot ROM Internal Memory Supports secure and regular Boot Modes. The ROM Controller supports ROM Patching. Table 4. i.MX50 Digital and Analog Modules (continued) Block Mnemonic Block Name Subsystem Brief Description |
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