MCIMX503CVM8B datasheet(20/134 Pages) FREESCALE

20 / 134 page

i.MX50 Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Electrical Characteristics

This section provides the device and module-level electrical characteristics of the i.MX50 processor.

NOTE

These electrical specifications are preliminary. These specifications are not

fully tested or guaranteed at this early stage of the product life cycle.

Finalized specifications are published after thorough characterization and

device qualifications have been completed.

USB_H1_VBUS,

USB_OTG_VBUS

These inputs are used by the i.MX50 to detect the presence and level of USB 5 V. If either

VBUS input pin is connected to an external USB connector, there is a possibility that a fast 5

V edge rate during a cable attach could trigger the VBUS input ESD protection, which could

result in damage to the i.MX50 silicon. To prevent this, the system should use some circuitry

to prevent the 5 V edge rate from exceeding 5.25 V / 1

μs. Freescale recommends the use of

a low pass filter consisting of 100

Ω resistor in series and a 1 μF capacitor close to the i.MX50

pin. In the case when the USB interface is connected on an on-board USB device (for example,

3G modem), the corresponding USB_VBUS pin may be left floating.

VREF

This pin is the DRAM MC reference voltage input. For LPDDR2 and DDR2, this pin should be

connected to ½ of NVCC_EMI_DRAM. For LPDDR1, this pin should be left floating. The user

may generate VREF using a precision external resistor divider. Use a 1 k

Ω 0.5% resistor to

GND and a 1 k

Ω 0.5% resistor to NVCC_EMI_DRAM. Shunt each resistor with a

closely-mounted 0.1 µF capacitor.

WDOG_B

This output can be used to reset the system PMIC when the i.MX50 processor is locked up.

This output is in the NVCC_MISC domain.

WDOG_RST_B_DEB

This output may be used to drive out the internal system reset signal to the system reset

controller. This is only intended for debug purposes.

XTAL/EXTAL

These pins are the 24 MHz crystal driver as well as the external 24 MHz clock input.

If using these pins to directly drive a 24 MHz crystal:

• The user should tie a 24 MHz fundamental-mode crystal across XTAL and EXTAL.

• The crystal must be rated for a maximum drive level of 100

μW or higher.

• The recommended crystal ESR (equivalent series resistance) is 80

Ω or less.

If using these pins as a clock input from an external 24 MHz oscillator:

• The crystal may be eliminated and EXTAL driven directly driven by the external oscillator.

The clock signal level on EXTAL must swing from NVCC_SRTC to GND.

• In this configuration, the XTAL pin must be floated and the COSC_EN bit (bit 12 in the CCR

bypass mode which allows EXTAL to be externally driven.

• Note there are strict jitter requirements if using an external oscillator in a USB application:

< 50 ps peak-to-peak below 1.2 MHz and < 100 ps peak-to-peak above 1.2 MHz for the

USB PHY.

Table 5. Special Signal Considerations (continued)

Signal Name

Remarks

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