MCIMX503CVM8B datasheet(2/134 Pages) FREESCALE

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i.MX50 Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Introduction

1.1

Product Overview

The i.MX50 is designed to enable high-tier portable applications by satisfying the performance

requirements of advanced operating systems and applications.

1.1.1

Dynamic Performance Scaling

Freescale’s dynamic voltage and frequency scaling (DVFS) allows the device to run at much lower voltage

and frequency with ample processing capacity for tasks, such as audio decode, resulting in significant

power reduction.

1.1.2

Multimedia Processing Powerhouse

The multimedia performance of the i.MX50 processor ARM Cortex-A8 core is boosted by a multi-level

cache system, a NEON co-processor with SIMD media processing architecture and 32-bit single-precision

floating point support, and two vector floating point co-processors. The system is further enhanced by a

programmable smart DMA (SDMA) controller.

1.1.3

Powerful Display System

The i.MX50 includes support for both standard LCD displays as well as electrophoretic displays (e-paper).

The display subsystem consists of the following modules:

•

Electrophoretic Display Controller (EPDC) (i.MX508 only)

The EPDC is a feature-rich, low power, and high-performance direct-drive active matrix EPD

controller. It is specifically designed to drive E-INKTM EPD panels, supporting a wide variety of

TFT architectures. The goal of the EPDC is to provide an efficient SoC integration of this

functionality for e-paper applications, allowing a significant bill of materials cost savings over an

external solution while reaching much higher levels of performance and lower power. The EPDC

module is defined in the context of an optimized hardware/software partitioning and works in

conjunction with the ePXP (see Section 1.1.4, “Graphics Accelerators”).

•

Enhanced LCD Controller Interface (eLCDIF)

The eLCDIF is a high-performance LCD controller interface that supports a rich set of modes and

allows interoperability with a wide variety of LCD panels, including DOTCK/RGB and smart

panels. The module also supports synchronous operation with the ePXP to allow the processed

frames to be passed from the ePXP to the eLCDIF through an on-chip SRAM buffer. The eLCDIF

can support up to 32-bit interfaces.

1.1.4

Graphics Accelerators

Integrated graphics accelerators offload processing from the ARM processor, enabling high performance

graphic applications at minimum power.

•

Pixel Processing Pipeline (ePXP)

The ePXP is a high-performance pixel processor capable of 1 pixel/clock performance for

combined operations, such as color-space conversion, alpha blending, gamma mapping, and

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