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MCIMX503CVM8B 数据表(PDF) 70 Page - Freescale Semiconductor, Inc |
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MCIMX503CVM8B 数据表(HTML) 70 Page - Freescale Semiconductor, Inc |
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70 / 134 page  i.MX50 Applications Processors for Consumer Products, Rev. 2 70 Freescale Semiconductor Electrical Characteristics NOTE DDR6 and DDR7 can be adjusted by the parameter -DLL_WR_DELAY-; The ideal case is that SDCLK is center aligned to the DRAM_A[9:0] data valid window; For this table, HW_DRAM_PHY23[14:8] (DLL_WR_DELAY) = 0x10; 4.8.3 DRAM Data Output Timing The DRAM data output timing is defined for all DDR types: DDR2, LPDDR1, and LPDDR2. Table 46. DDR Output AC Timing ID Description Symbol Min Max Unit DDR10 Positive DQS latching edge to associated CK edge tDQSS -0.3 0.3 ns DDR11 DQS falling edge from CK rising edge—hold time tDSH 0.5 tCK - 0.3 0.5 tCK + 0.3 ns DDR12 DQS falling edge to CK rising edge—setup time tDSS 0.5 tCK - 0.3 0.5 tCK + 0.3 ns DDR13 DQS output high pulse width tDQSH 0.48 tCK 0.52 tCK ns DDR14 DQS output low pulse width tDQSL 0.48 tCK 0.52 tCK ns DDR15 CK >= 200 MHz DQ & DQM output setup time relative to DQS tDS 0.5 tCK - 1.3 —ns Figure 30. DRAM Data Output Timing DRAM_SDCLK DRAM_SDCLK_B DRAM_SDQS DDR13 DDR14 d0 DDR10 d1 d2 d3 DRAM_D & DRAM_DQM DDR11 DDR12 DDR15 DDR16 DRAM_SDQS_B |
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