MCIMX503CVM8B datasheet(114/134 Pages) FREESCALE

114 / 134 page

i.MX50 Applications Processors for Consumer Products, Rev. 2

114

Freescale Semiconductor

Package Information and Contact Assignments

NVCC_RESET

—

NVCC_SD1

—

NVCC_SD2

—

NVCC_SPI

—

NVCC_SRTC

AA1

—

NVCC_SSI

—

NVCC_UART

—

POP_EMMC_RST

A19

This is PoP eMMC 4.4 NAND Reset

input pin. This pin does not connect to

the i.MX50. If using eMMC 4.4 NAND,

this pin can be connected to a GPIO.

For non 4.4 eMMC applications, leave

floating.

POP_LPDDR2_1.8V

A20, B19, B20, M5, N5

This is the 1.8V supply for the PoP

LPDDR2. These pins do not connect to

the i.MX50.

POP_LPDDR2_ZQ0

AA24

This is the PoP LPDDR2 ZQ0 pin. This

pin does not connect to the i.MX50.

This should be connected on the PCB

to a 240

Ω 1% resistor to ground

POP_LPDDR2_ZQ1

AA23

This is the PoP LPDDR2 ZQ1 pin. This

pin does not connect to the i.MX50. If

used, this should be connected on the

PCB to a 240

Ω 1% resistor to ground

POP_NAND_VCC

D19, D20

This is the 3.3V I/O and memory supply

for the PoP eMMC NAND. Note that

because the eMMC memory and I/O

domains are shorted together, it is not

possible to support 1.8 V I/O for the PoP

eMMC NAND.

USB_VDDA25

AC9, AD9

Note that on the PoPBGA package,

USB_OTG_VDDA25 and

USB_H1_VDDA25 are shorted

together.

USB_VDDA33

AC11, AD11

Note that on the PoPBGA package,

USB_OTG_VDDA33 and

USB_H1_VDDA33 are shorted

together.

VCC

H14, H15, H16, H17, J17, K14, K15, K17, L15

—

VDD_DCDCI

—

VDD_DCDCO

—

VDD1P2

AD6

—

VDD1P8

AD7

—

Table 81. 416 PoPBGA 13 x 13 mm Ground, Power, Sense, and Reference Contact Signals (continued)

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