MCIMX503CVM8B datasheet(133/134 Pages) FREESCALE

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Revision History

i.MX50 Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

133

Revision History

Table 85 provides a revision history for this data sheet.

Table 85. i.MX50 Data Sheet Document Revision History

Rev.

Number

Date

Substantive Change(s)

Rev. 2

05/2012

• In Table 1, "Ordering Information," on page 7, added the following new part numbers: MCIMX508CZK8B,

MCIMX503CVK8B, MCIMX503EVM8B, MCIMX502CVK8B, and MCIMX502EVM8B.

•In Table 1, "Ordering Information," on page 7, added a new column, Tjunction.

•In Table 3, "Package Feature Comparison," on page 8, added a new row for 416 PoPBGA package.

• Updated Figure 1, "i.MX50 System Block Diagram," on page 10 by removing “LDOx3” and “DC-DC 1.2V.”

•In Table 5, "Special Signal Considerations," on page 17, updated details for the following signals:

DRAM_OPEN/DRAM_OPENFB and DRAM_SDODT0/DRAM_SDODT1

•In Table 5, "Special Signal Considerations," on page 17, added new rows for the following signals:

POP_EMMC_RST, POP_LPDDR2_ZQ0/ZQ1, POP_LPDDR2_1.8V, and POP_NAND_VCC.

• Added Section 4.1.2.1, “13 x 13 mm MAPBGA Package Thermal Resistance Data.”

• Added Section 4.1.2.2, “13 x 13 mm PoPBGA Package Thermal Resistance Data.”

• Added Section 4.1.2.3, “17 x 17 mm MAPBGA Package Thermal Resistance Data.”

•In Table 11, "i.MX50 Operating Ranges," on page 24, added footnotes for USB_OTG_VDDA25 and

USB_OTG_VDDA33.

•In Table 77, "VBUS Comparators Thresholds," on page 100, changed VBUS input max current to 350

μA.

• Added Section 5.2, “13 x 13 mm, 0.5 mm Pitch, 416 Pin PoPBGA Package Information.”

•In Table 84, "Alphabetical List of Signal Assignments," on page 123:

—Added a new column “416 PoPBGA Ball Number”

—Changed “USB_H1_VDDA” to “USB_H1_VDDA25, USB_H1_VDDA33”

—Changed “USB_OTG_VDDA” to “USB_OTG_VDDA25, USB_OTG_VDDA33”

• Replace mDDR with LPDDR1 throughout the document.

Rev. 1

10/2011

• Table 5, "Special Signal Considerations," on page 17 changed CHRG_DET_B to CHGR_DET_B.

• Table 5, "Special Signal Considerations," on page 17 in the CHGR_DET_B signal remarks, added “The

maximum current leakage at this pin is 8.5

μA.”

• Table 5, "Special Signal Considerations," on page 17 in the JTAG_MOD remarks, changed “pull-down”

to “pull-up, by default” and added “If JTAG port is not needed, the internal pull-up can be disabled in order

to reduce supply current to the pin.”

• Table 14, "Maximum Supply Current Consumption," on page 27 in the 11th row under the Supply column,

changed VDDO2P5 to VDDO25.

• Table 77, "VBUS Comparators Thresholds," on page 100 changed CHRG_DET_B to CHGR_DET_B.

• Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDCLK_0 pin number

was changed to N24 and DRAM_SDCLK_0_B pin number was changed to M24.

• Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDCLK_1 pin number

was changed to T20 and DRAM_SDCLK_1_B pin number was changed to R20.

• Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDQS0 pin number was

changed to P23 and DRAM_SDQS0_B pin number was changed to P24.

• Table 5, "Special Signal Considerations," on page 17 changed pad type of pin DRAM_CALIBRATION to

DRAMCALIB.

• Table 5, "Special Signal Considerations," on page 17 changed pad type of pins DRAM_SDCLK_0,

DRAM_SDCLK_0_B, DRAM_SDCLK_1, DRAM_SDCLK_1_B, DRAM_SDQS0, DRAM_SDQS0_B,

DRAM_SDQS1, DRAM_SDQS1_B, DRAM_SDQS2, DRAM_SDQS2_B, DRAM_SDQS3, and

DRAM_SDQS3_B to DRAMCLK.

Rev. 0

07/2011 Initial release.

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