AN983 datasheet(22/91 Pages) ETC

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AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

7.1.3 AN983B CONFIGURATION REGISTERS DESCRIPTIONS

CR0 (offset = 00h), LID - Loaded Identification number of Device and Vendor

Bit #

Name

Descriptions

Default Val RW Type

31~16

LDID

Loaded Device ID, the device ID number loaded from serial

EEPROM.

From

EEPROM

R/O

15~0

LVID

Loaded Vendor ID, the vendor ID number loaded from serial

EEPROM.

From

EEPROM

R/O

From EEPROM: Loaded from EEPROM

CR1 (offset = 04h), CSC - Configuration command and status

Bit #

Name

Descriptions

Default Val RW Type

SPE

Status of Parity Error.

1: means that AN983B detected a parity error. This bit will

be set in this condition, even if the parity error response (bit

6 of CR1) is disabled.

R/W

SES

Status of System Error.

1: means that AN983B asserted the system error pin.

R/W

SMA

Status of Master Abort.

1: means that AN983B received a master abort and

terminated a master transaction.

R/W

STA

Status of Target Abort.

1: means that AN983B received a target abort and

terminated a master transaction.

R/W

---

Reserved.

26, 25

SDST

Status of Device Select Timing. The timing of the assertion of

device select.

01: means a medium assertion of DEVSEL#

R/O

SDPR

Status of Data Parity Report.

1: when three conditions are met:

AN983B asserted parity error - PERR# or it detected parity

error asserted by other device.

AN983B is operating as a bus master.

AN983B’s parity error response bit (bit 6 of CR1) is enabled.

R/W

SFBB

Status of Fast Back-to-Back

Always 1, since AN983B has the ability to accept fast

back-to-back transactions.

R/O

22~21

---

Reserved.

New Capabilities. This bit indicates that whether the AN983B

provides a list of extended capabilities, such as PCI power

management.

Same as

bit 19 of

CSR18

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

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