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AN983 数据表(PDF) 24 Page - List of Unclassifed Manufacturers |
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AN983 数据表(HTML) 24 Page - List of Unclassifed Manufacturers |
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24 / 91 page ![]() AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY timer expires and the AN983B still asserted FRAME#, then the AN983B will terminate the data transaction as soon as its GNT# is removed. 7 ~ 0 CLS Cache Line Size. This value specifies the system cache line size in units of 32-bit double words (DW). The AN983B supports 8, 16, and 32 DW of cache line size. This value is used by the AN983B driver to program the cache alignment bits (bit 14 and 15 of CSR0). The cache alignment bits are used for cache oriented PCI commands; say memory-read-line, memory-read-multiple, and memory-write-and-invalidate. 0 R/W CR4 (offset = 10h), IOBA - I/O Base Address Bit # Name Descriptions Default Val RW Type 31~ 8 IOBA I/O Base Address. This value indicate the base address of PCI control and status register (CSR0~28) 0 R/W 7 ~ 1 --- Reserved. 0 IOSI I/O Space Indicator. 1: means that the configuration registers map into the I/O space. 1 RO CR5 (offset = 14h), MBA - Memory Base Address Bit # Name Descriptions Default Val RW Type 31~ 10 MBA Memory Base Address. This value indicate the base address of PCI control and status register (CSR0~28) 0 R/W 9 ~ 1 --- Reserved. 0 IOSI Memory Space Indicator. 1: means that the configuration registers map into the I/O space. 0 RO CR11 (offset = 2ch), SID - Subsystem ID. Bit # Name Descriptions Default Val RW Type 31~16 SID Subsystem ID. This value is loaded from EEPROM after power on or hardware reset. From EEPROM RO 15~ 0 SVID Subsystem Vendor ID. This value is loaded from EEPROM after power on or hardware reset. From EEPROM RO CR12 (offset = 30h), BRBA - Boot ROM Base Address. Bit # Name Descriptions Default Val RW Type 31~17 BRBA Boot ROM Base Address. This value indicates the address mapping of boot ROM field. Besides, it also defines the boot ROM size. The value of bit 17~10 is set to 0 for AN983B supports up to 256KB of boot ROM. X: b31~18 0: b17~10 R/W RO 16 ~ 1 --- Reserved 0 RO R/W ADMtek Inc. www.admtek.com.tw Rev. 1.8 24 |
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