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AN983 数据表(PDF) 63 Page - List of Unclassifed Manufacturers |
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AN983 数据表(HTML) 63 Page - List of Unclassifed Manufacturers |
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63 / 91 page ![]() AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY 8.4 RECEIVE SCHEME AND RECEIVE EARLY INTERRUPT SCHEME The following figure shows the difference of timing without early interrupt and with early interrupt. handled by driver handled by AN983B incoming packet receive FIFO operation FIFO-to-host memory operation interrupt driver read header higher layer process driver read the rest data time receive early interrupt driver read header(early) higher layer process(early) driver read the rest data finish time finish time Fig - 12 Receive data flow (without early interrupt and with early interrupt) ADMtek Inc. www.admtek.com.tw Rev. 1.8 63 |
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