AN983 datasheet(27/91 Pages) ETC

27 / 91 page

AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

interpreting the value of the Data register. This field is

required for any function that implements the Data register.

Otherwise, it’s optional.

The AN983B doesn’t support Data register and Data_Scale.

12~9

DSEL

Data_Select, This four-bit field is used to select which data

is to be reported through the Data register and Data_Scale

field. This field is required for any function that implements

the Data register.

The AN983B doesn’t support Data_select.

0000b

R/W

PME_En

PME_En, “1” enables the AN983B to assert PME#. When “0”

disables the PME# assertion.

Magic packet default enable:

When Csr18<18> and csr18<19> are set to 1, than the magic

packet wake up event will be default enabled (csr13<9> be

set) it doesn’t matter the PME_En is set or not.

R/W

7~2

---

Reserved.

000000b

1,0

PWRS

PowerState, This two-bit field is used both to determine the

current power state of the AN983B and to set the AN983B

into a new power state. The definition of this field is given

below.

00b - D0

01b - D1

10b - D2

11b - D3hot

This field is auto cleared to D0 when power resumed.

00b

R/W

R/W*: Read and Write clear

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

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