AN983 datasheet(68/91 Pages) ETC

68 / 91 page

AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

cabling. So a reliable adaptive equalizer and baseline wander to compensate all the

amplitude attenuation and phase shifting are necessary. In the transceiver, it

provides the robust circuits to perform these functions.

MLT3 to NRZI Decoder and PLL for Data Recovery

After receiving the proper MLT3 signals, the transceiver converts the MLT3 to NRZI

code for further processing. After adaptive equalizer, baseline wander, and MLT3 to

NRZI decoder, the compensated signals with NRZI type in 125MHz are passed to the

Phase Lock Loop circuits to extract out the original data and the synchronous clock.

Data Conversions of NRZI to NRZ and Serial to Parallel

After data recovered, the signals will be passed to the NRZI to NRZ converter to

generate the 125MHz serial bit stream. This serial bit stream will be packed to

parallel 5B type for further processing.

De-scrambling and Decoding of 5B/4B

The parallel 5B type data is passed to de-scrambler and 5B/4B decoder to return their

original MII nibble type data.

Carrier sensing

Carrier Sense (CRS) signal is asserted when the transceiver detects any 2

non-contiguous zeros within any 10bit boundary of the receiving bit stream. CRS is

de-asserted when ESD code-group or Idle code-group is detected. In half duplex mode,

CRS is asserted during packet transmission or receive. But in full duplex mode, CRS is

asserted only during packet reception.

10BASE-T Transmission Operation

It includes the parallel to serial converter, Manchester Encoder, Link test function, Jabber

function and the transmit wave-shaper and line driver described in the section of

“Wave-Shaper and Media Signal Driver” of “100BASE-T Transmission Operation”.

It also

provides Collision detection and SQE test for half duplex application.

10BASE-T Receive Operation

It includes the carrier sense function, receiving filter, PLL for clock and data recovering,

Manchester decoder, and serial to parallel converter.

Loop-back Operation of transceiver

The transceiver provides internal loop-back (also called transceiver loop-back) operation for

both the 100BASE-TX and 10BASE-T operations. Setting bit 14 of PHY register 0 to 1 can

enable the loop-back operation.

In this loop-back operation, PHY will not transmit packets

(but PHY will still send MLT3 for Idle).

In the 100BASE-TX internal loop-back operation, the data comes from the transmit output of

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

AN983 数据表(PDF) 68 Page - List of Unclassifed Manufacturers

AN983 数据表(HTML) 68 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

数据表下载