AN983 datasheet(48/91 Pages) ETC

48 / 91 page

AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

When set inhibits actual transmission on the wire.

Speed selection

Forces speed of Phy only when autonegotiation is disabled. The default state of this

bit will be determined by a power-up configuration pin in this case. Otherwise it

defaults to 1.

Auto-neg enable Defaults to pin programmed value. When cleared allows forcing

of speed and duplex settings. When set (after being cleared) causes re-start of

autoneg process. Pin programming at power-up allows it to come up disabled and

for software to write the desired capability before allowing the first negotiation to

commence.

Restart Negotiation

only has effect when autonegotiating. Restarts state machine.

Power down

Has no effect in this device. Test mode power down modes may be implemented in

other specific modules.

Isolate

Puts RMII receive signals into high impedance state and

ignores transmit signals.

Duplex mode

When bit12 is cleared (i.e. autoneg disabled), this bit forces full duplex (bit = 1) or

half duplex (bit = 0).

Collision test

Always 0 because collision signal is not implemented.

BIT

NAME

DESCRIPTION

Read/Write

Default

100 BASE T4

Not supported

100BASE-X Full

Duplex

1 = PHY is 100BASE-X full duplex

capable

0 = PHY is not 100BASE-X full duplex

capable

100BASE-X Half

Duplex

1 = PHY is 100BASE-X half duplex capable

0 = PHY is not 100BASE-X half duplex

capable

10Mbps/s Full

Duplex

1 = PHY is 10Mbps/s Full duplex capable

0 = PHY is not 10Mbps/s Full duplex

capable

10 Mb/s Half

Duplex

1 = PHY is 10Mbps/s Half duplex capable

0 = PHY is not 10Mbps/s Half duplex

capable

100BASE-T2 full

duplex

Not supported

100BASE-T2 half

Not supported

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

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