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AN983 数据表(PDF) 53 Page - List of Unclassifed Manufacturers

部件名 AN983
功能描述  PCI/miniPCI-to-Ethernet LAN Controller
PDF  91 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

AN983 数据表(HTML) 53 Page - List of Unclassifed Manufacturers

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AN983B
PCI/miPCI Fast Ethernet Controller with integrated PHY
9
FS
First descriptor.
8
LS
Last descriptor.
7
TL
Too long packet (packet length > 1518 bytes). This bit is valid only in last descriptor
6
CS
Late collision. Set when collision is active after 64 bytes. This bit is valid only in last
descriptor
5
FT
Frame type. This bit is valid only in last descriptor.
1: Ethernet type
0: 802.3 type
4
RW
Receive watchdog (refer to CSR15, bit 4). This bit is valid only in last descriptor.
3
Reserved Default = 0
2
DB
Dribble bit. This bit is valid only in last descriptorEC
Packet length is not integer multiple of 8-bit.
1
CE
CRC error. This bit is valid only in last descriptor
0
OF
Overflow. This bit is valid only in last descriptor
RDES1
Bit #
Name
Descriptions
31~26
---
Reserved
25
RER
Receive end of ring
Indicates this descriptor is last, return to base address of descriptor
24
RCH
Second address chain
Use for chain structure. Indicates the buffer2 address is the next descriptor address.
Ring mode takes precedence over chained mode
23~22
---
Reserved
21~11
RBS2
Buffer 2 size (DW boundary)
10~ 0
RBS1
Buffer 1 size (DW boundary)
RDES2
Bit #
Name
Descriptions
31~0
RBA1
Receive Buffer Address 1. This buffer address should be double word aligned.
RDES3
Bit #
Name
Descriptions
31~0
RBA2
Receive Buffer Address 2. This buffer address should be double word aligned.
7.4.2. TRANSMIT DESCRIPTOR
7.4.2.1. Transmit Descriptor Table
31
0
ADMtek Inc.
www.admtek.com.tw
Rev. 1.8
53



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