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AN983 数据表(PDF) 61 Page - List of Unclassifed Manufacturers |
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AN983 数据表(HTML) 61 Page - List of Unclassifed Manufacturers |
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61 / 91 page ![]() AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY 8.3 TRANSMIT SCHEME AND TRANSMIT EARLY INTERRUPT 8.3.1 TRANSMIT FLOW The flow of packet transmit is shown as below. Initial End Program the descriptor, and place data into the host memory Change own bit to 1 Write tx demand poll AN983B read descriptor Yes No no deferring and greater than tx threshold DO TRANSMIT read the rest data collision ? write descriptor generate interrupt own=0 available descriptor(own=1) read data and put into tx fifo back -off Fig - 9 Transmit flow 8.3.2 TRANSMIT PRE-FETCH DATA FLOW Transmit FIFO size=2K-byte Two packets in the FIFO at the same time Meet the transmit min. back-to-back ADMtek Inc. www.admtek.com.tw Rev. 1.8 61 |
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