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AN983 数据表(PDF) 35 Page - List of Unclassifed Manufacturers |
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AN983 数据表(HTML) 35 Page - List of Unclassifed Manufacturers |
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35 / 91 page ![]() AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY 1: combine this bit and bit 16 of CSR7 to enable receive completed interrupt. 5 TUIE Transmit Under-flow Interrupt Enable 1: combine this bit and bit 15 of CSR7 to enable transmit under-flow interrupt. 0 R/W 4 --- Reserved 3 TJTTIE Transmit Jabber Timer Time-out Interrupt Enable 1: combine this bit and bit 15 of CSR7 to enable transmit jabber timer time-out interrupt. 0 R/W 2 TDUIE Transmit Descriptor Unavailable Interrupt Enable 1: combine this bit and bit 16 of CSR7 to enable transmit descriptor unavailable interrupt. 0 R/W 1 TPSIE Transmit Processor Stopped Interrupt Enable 1: combine this bit and bit 15 of CSR7 to enable transmit processor stopped interrupt. 0 R/W 0 TCIE Transmit Completed Interrupt Enable 1: combine this bit and bit 16 of CSR7 to enable transmit completed interrupt. 0 R/W CSR8 (offset = 40h), LPC - Lost packet counter Bit # Name Descriptions Default Val RW Type 31~17 --- Reserved 16 LPCO Lost Packet Counter Overflow 1: while lost packet counter overflowed. Cleared after read 0 RO/LH 15~0 LPC Lost Packet Counter Increment the counter while packet discarded since there was no host receives descriptors available. Cleared after read 0 RO/LH CSR9 (offset = 48h), SPR - Serial port register Bit # Name Descriptions Default Val RW Type 31~20 --- Reserved 19 MDI MII Management Data Input Specified read data from the external PHY 0 R/W 18 MMC MII Management Control 0: Write operation to the external PHY 1: Read operation from the external PHY 1 R/W 17 MDO MII Management Data Output Specified Write Data to the external PHY 0 R/W 16 MDC MII Management Clock 1: MII Management Clock is a output reference clock to the external PHY 0 R/W ADMtek Inc. www.admtek.com.tw Rev. 1.8 35 |
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