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AN983 数据表(PDF) 39 Page - List of Unclassifed Manufacturers |
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AN983 数据表(HTML) 39 Page - List of Unclassifed Manufacturers |
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39 / 91 page ![]() AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY watchdog timer from last carrier deserted. 0: 24 bit-time 1: 48 bit-time 4 RWD Receive Watchdog Disable 0: If the receiving packet‘s length is longer than 2560 bytes, the watchdog timer will be expired. 1: disable the receive watchdog. 0 R/W 3 --- Reserved 2 JCLK Jabber clock 0: cut off transmission after 2.6 ms (100Mbps) or 26 ms (10Mbps). 1: cut off transmission after 2560 byte-time. 0 R/W 1 NJ Non-Jabber 0: if jabber expired, re-enable transmit function after 42 ms (100Mbps) or 420ms (10Mbps) 1: immediately re-enable the transmit function after jabber expired 0 R/W 0 JBD Jabber disable 1: disable transmit jabber function 0 R/W CSR16 (offset = 80h), ACSR5 - Assistant CSR5 (Status register 2) Bit # Name Descriptions Default Val RW Type 31 TEIS Transmit Early Interrupt status Transmit early interrupt status is set to 1 when Transmit early interrupt function is enabled (set bit 31 of CSR17 = 1) and the transmitted packet is moved completed from descriptors to TX-FIFO buffer. This bit is cleared by written with 1. 0 RO/LH* 30 REIS Receive Early Interrupt Status. Receive early interrupt status is set to 1 when Receive early interrupt function is enabled (set bit 30 of CSR17 = 1) and the received packet is fill up its first receive descriptor. This bit is cleared by written with 1. 0 RO/LH* 29 LCS Status of Link status change 0 RO/LH* 28 TDIS Transmit Deferred Interrupt Status. 0 RO/LH* 27 --- Reserved 26 PFR PAUSE Frame Received Interrupt Status 1: indicates a PAUSE frame received when the PAUSE function is enabled. 0 RO/LH* 25~17 --- Reserved 16 ANISS Added normal interrupt status summary. 1: any of the added normal interrupts happened. 0 RO/LH* ADMtek Inc. www.admtek.com.tw Rev. 1.8 39 |
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