AN983 datasheet(69/91 Pages) ETC

69 / 91 page

AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

NRZ to NRZI converter then loop-back to the receive path into the input of NRZI to NRZ

converter.

In the 10BASE-T loop-back operation, the data is through transmitting path and loop-back

from the output of the Manchester encoder into the input of Phase Lock Loop circuit of

receive path.

Full Duplex and Half Duplex Operation of Transceiver

The transceiver can operate for either full duplex or half duplex network application. In full duplex,

both transmit and receive can be operated simultaneously. Under full duplex mode, collision (COL)

signal is ignored and carrier sense (CRS) signal is asserted only when the transceiver is receiving.

In half duplex mode, either transmit or receive can be operated at one time. Under half duplex mode,

collision signal is asserted when transmit and receive signals collided and carrier sense asserted

during transmission and reception.

Auto-Negotiation Operation

The Auto-Negotiation function is designed to provide the means to exchange information

between the transceiver and the network partner to automatically configure both to take

maximum advantage of their abilities, and both are setup accordingly. The Auto-Negotiation

function can be controlled through bit 12 of PHY register 0.

The Auto-Negotiation exchanges information with the network partner using the Fast Link

Pulses (FLPs) - a burst of link pulses. There are 16 bits of signaling information contained in

the burst pulses to advertise all remote partners’ capabilities, which are determined by PHY,

following the priority sequence as below:

1. 100BASE-TX full duplex

2. 100BASE-TX half duplex

3. 10BASE-T full duplex

4. 10BASE-T half duplex

During power-up or reset, if Auto-Negotiation is found enabled then FLPs will be transmitted

and the Auto-Negotiation function will process. Otherwise, the Auto-Negotiation will not

occur until the bit 12 of PHY register 0 is set to 1.

When the Auto-Negotiation is disabled,

then the Network Speed and Duplex Mode are selected by programming PHY register 0.

Power Down Operation

To reduce the power consumption the transceiver is designed with power down feature,

which can save the power consumption significantly. Since the power supply of the

100BASE-TX and 10BASE-T circuits are separated, the transceiver can turn off the circuit of

either the 100BASE-TX or 10BASE-T when the other one of them is operating.

8.5.3 FLOW CONTROL IN FULL DUPLEX APPLICATION

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

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