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AN983 数据表(PDF) 43 Page - List of Unclassifed Manufacturers

部件名 AN983
功能描述  PCI/miniPCI-to-Ethernet LAN Controller
PDF  91 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

AN983 数据表(HTML) 43 Page - List of Unclassifed Manufacturers

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AN983B
PCI/miPCI Fast Ethernet Controller with integrated PHY
effect.
Since the AN983B doesn’t supports PME# from D3cold, this
bit is defaulted to “0”.
14,13
DSCAL
Data_Scale, indicates the scaling factor to be used when
interpreting the value of the Data register. This field is
required for any function that implements the Data register.
Otherwise, it’s optional.
The AN983B doesn’t support Data register and Data_Scale.
00b
RO
12~9
DSEL
Data_Select, This four bit field is used to select which data is
to be reported through the Data register and Data_Scale
field. This field is required for any function that implements
the Data register.
The AN983B doesn’t support Data_select.
0000b
RO
8
PME_En
PME_En, “1” enables the AN983B to assert PME#. When “0”
disables the PME# assertion.
This bit defaults to “0” if the function does not support PME#
generation from D3cold.
0
RO
7~2
---
Reserved.
000000b
RO
1,0
PWRS
PowerState, This two bit field is used both to determine the
current power state of the AN983B and to set the AN983B
into a new power state. The definition of this field is given
below.
00b - D0
01b - D1
10b - D2
11b - D3hot
If software attempts to write an unsupported, optional state
to this field, the write operation must complete normally on
the bus, however the data is discarded a no state change
occurs.
00b
RO
CSR21 (offset = 94h) - WTDP, The current working transmit descriptor pointer
Bit #
Name
Descriptions
Default Val RW Type
31~0
WTDP
The current working transmit descriptor pointer for driver’s
double-checking or other special purpose.
XXXX
RO
CSR22 (offset = 98h) - WRDP, The current working receive descriptor pointer
Bit #
Name
Descriptions
Default Val RW Type
31~0
WRDP
The current working receive descriptor pointer for driver’s
double-checking or other special purpose.
XXXX
RO
CSR23 (offset = 9ch) - TXBR, transmit burst count / time-out
Bit #
Name
Descriptions
Default Val RW Type
31~21
---
Reserved
ADMtek Inc.
www.admtek.com.tw
Rev. 1.8
43



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