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AN983 数据表(PDF) 47 Page - List of Unclassifed Manufacturers

部件名 AN983
功能描述  PCI/miniPCI-to-Ethernet LAN Controller
PDF  91 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

AN983 数据表(HTML) 47 Page - List of Unclassifed Manufacturers

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AN983B
PCI/miPCI Fast Ethernet Controller with integrated PHY
7.3. PHY REGISTERS (ACCESSED BY CSR9
MDI/MMC/MDO/MDC)
7.3.1. TRANSCEIVER REGISTERS DESCRIPTIONS
Register 0 (MII Control)
BIT
NAME
DESCRIPTION
Read/Write
DEFAULT
15
Reset
1 = PHY Reset
0 = normal operation
R/W, SC
0
14
Loopback
1 = enable loopback
0 = disable loopback
R/W
0
13
Speed selection
1 = 100Mbps/s
0 = 10 Mb/s
R/W
Pin - see note
12
Autonegotiation enable
1 = enable autoneg
0 = disable autoneg
R/W
Pin – see note
11
Power down
1 = Power Down
0 = normal operation
R/W
0
10
Isolate
1 = isolate PHY from MII
0 = normal operation
R/W
0
9
Restart autonegotiation
1 = Restart Autoneg
R/W, SC
0
8
Duplex mode
1 = full, 0 = half
R/W
Pin – see note
7
Collision test
Not implemented
RO
0 - see note
6:0
Reserved
RO
0000000
SC
Self Clearing
Reset
Reset this port only. This will cause the following:
1. Restart the autonegotiation process.
2. Reset the registers to their default values. Note that this does not affect registers
20, 22, 30 or 31. These registers are not reset by this bit to allow test configurations
to be written and then not affected by resetting the port.
Note: No reset is performed to analogue sections of the port. There is also no physical reset to any
internal clock synthesisers or the local clock recovery oscillator which will continue to run throughout
the reset period. However since the port is restarted and autoneg re-run the process of locking the
frequency of the local oscillator (slave) to the reference oscillator (master) will be repeated as it is at
the start of any link initialization process.
Loopback
Loop back of transmit data to receive via a path as close to the wire as possible.
ADMtek Inc.
www.admtek.com.tw
Rev. 1.8
47



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