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AN983 数据表(PDF) 23 Page - List of Unclassifed Manufacturers

部件名 AN983
功能描述  PCI/miniPCI-to-Ethernet LAN Controller
PDF  91 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

AN983 数据表(HTML) 23 Page - List of Unclassifed Manufacturers

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AN983B
PCI/miPCI Fast Ethernet Controller with integrated PHY
1: the AN983B provides the PCI management function
0: the AN983B doesn’t provide New Capabilities.
19~ 9
---
Reserved.
8
CSE
Command of System Error Response
1: enable system error response. AN983B will assert SERR#
When it find a parity error on the address phase.
0
R/W
7
---
Reserved.
6
CPE
Command of Parity Error Response
0: disable parity error response. AN983B will ignore any
detected parity error and keep on its operating. Default
value is 0.
1: enable parity error response. AN983B will assert system
error (bit 13 of CSR5) when a parity error is detected.
0
R/W
5~ 3
---
Reserved.
2
CMO
Command of Master Operation Ability
0: disable the bus master ability.
1: enable the PCI bus master ability. Default value is 1 for
normal operation.
0
R/W
1
CMSA
Command of Memory Space Access
0: disable the memory space access ability.
1: enable the memory space access ability.
0
R/W
0
CIOSA
Command of I/O Space Access
1: enable the I/O space access ability.
0: disable the I/O space access ability.
0
R/W
R/W: Read and Write able. RO: Read able only.
CR2 (offset = 08h), CC - Class Code and Revision Number
Bit #
Name
Descriptions
Default Val RW Type
31~24
BCC
Base Class Code. It means AN983B is network controller.
02h
RO
23~16
SC
Subclass Code. It means AN983B is a Fast Ethernet
Controller.
00h
RO
15~ 8
---
Reserved.
7 ~ 4
RN
Revision Number identifies the revision number of AN983B.
01h
RO
3 ~ 0
SN
Step Number, identifies the AN983B steps within the current
revision.
01h
RO
RO: Read Only.
CR3 (offset = 0ch), LT - Latency Timer
Bit #
Name
Descriptions
Default Val RW Type
31~16
---
Reserved.
15~ 8
LT
Latency Timer. This value specifies the latency timer of the
AN983B in units of PCI bus clock. Once the AN983B asserts
FRAME#, the latency timer starts to count. If the latency
0
R/W
ADMtek Inc.
www.admtek.com.tw
Rev. 1.8
23



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