| 数据搜索系统,热门电子元器件搜索 |
|
AN983 数据表(PDF) 45 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
AN983 数据表(HTML) 45 Page - List of Unclassifed Manufacturers |
|
45 / 91 page ![]() AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY For example, physical address = 00-00-e8-11-22-33 PAR0= 11 e8 00 00 PAR1= xx xx 33 22 PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bit19-17=000). CSR27 (offset = ach) - MAR0, multicast address register 0 Bit # Name Descriptions Default Val RW Type 31~24 MAB3 Multicast address byte 3 (hash table 31:24) 0 R/W 23~16 MAB2 Multicast address byte 2 (hash table 23:16) 0 R/W 15~8 MAB1 Multicast address byte 1 (hash table 15:8) 0 R/W 7~0 MAB0 Multicast address byte 0 (hash table 7:0) 0 R/W CSR28 (offset = b0h) - MAR1, multicast address register 1 Bit # Name Descriptions Default Val RW Type 31~24 MAB7 Multicast address byte 7 (hash table 63:56) 0 R/W 23~16 MAB6 Multicast address byte 6 (hash table 55:48) 0 R/W 15~8 MAB5 Multicast address byte 5 (hash table 47:40) 0 R/W 7~0 MAB4 Multicast address byte 4 (hash table 39:32) 0 R/W MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bit19-17=000). Multicast 64 Algorithm: AN983B uses CRC [5:0] to hit one of the 64 entries in UMAR1 [31:0] and MAR0[31:0] by generated CRC32 from Ethernet DA (destination address). The most significant bit CRC [5] choose the upper or lower double word, (MAR1 or MAR0), the lower 5 bit present for the corresponding bit inside the double word. Example 1: If CRC [5] =1'b0 --> hit MAR0 CRC [4:0] = 5'b00010 --> hit MAR0 [2] Example 2: CRC [5] = 1'b1 --> hit MAR1 CRC [4:0] = 5'b00100--> hit MAR1 [4] CSR_29 (offset = b4h) - UAR0, unicast address register 0 Bit # Name Descriptions Default Val RW Type 31~24 UAB3 Unicast address byte 3 (hash table 31:24) 0 R/W 23~16 UAB2 Unicast address byte 2 (hash table 23:16) 0 R/W 15~8 UAB1 Unicast address byte 1 (hash table 15:8) 0 R/W 7~0 UAB0 Unicast address byte 0 (hash table 7:0) 0 R/W ADMtek Inc. www.admtek.com.tw Rev. 1.8 45 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |