AN983 datasheet(49/91 Pages) ETC

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AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

duplex

8-7

Reserved

MF Preamble

Suppression

1 = PHY can accept management frames

with preamble suppression

0 = PHY cannot accept management

frames with preamble suppression

Autoneg Complete

1 = autoneg completed,

0 = autoneg incomplete

Remote Fault

1 = remote fault detected,

0 = no remote fault detected

RO, LH

Autoneg Ability

1 = PHY can auto-negotiate,

0 = PHY cannot auto-negotiate

Link Status

1 = link is up,

0 = link is down

RO, LL

Jabber Detect

1 = jabber condition detected

RO, LH

0(see note)

Extended

Capability

1 = extended register capabilities,

0 = basic register set capabilities only

Latch Low

Latch High

Jabber detect

Only used in 10Base-T mode. Reads as 0 in 100Base-TX mode.

Each PHY has an identifier, which is assigned to the device.

The identifier contains a total of 32 bits, which consists of the following: 22 bits of a 24bit organisationally

unique identifier (OUI) for the manufacturer; a 6-bit manufacturer’s model number; a 4-bit manufacturer’s

revision number. For an explanation of how the OUI maps to the register, please refer to IEEE 802-1990

clause 5.1

BIT

NAME

DESCRIPTION

READ/WRITE

DEFAULT

15:0

PHY_ID[31-16]

OUI (bits 3-18)

001D(Hex)

BIT

NAME

DESCRIPTION

READ/WRITE

DEFAULT

15:1

PHY_ID[15-10]

OUI (bits 19-24)

001001(bin)

9:4

PHY_ID[9-4]

Manufacturer’s Model Number

000001(bin)

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

AN983 数据表(PDF) 49 Page - List of Unclassifed Manufacturers

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