| 数据搜索系统,热门电子元器件搜索 |
|
AN983 数据表(PDF) 32 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
AN983 数据表(HTML) 32 Page - List of Unclassifed Manufacturers |
|
32 / 91 page ![]() AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY 12 --- Reserved 11 GPTT General Purpose Timer Time-out, base on CSR11 timer register 0 RO/LH* 10 --- Reserved 9 RWT Receive Watchdog Time-out, based on CSR15 watchdog timer register 0 RO/LH* 8 RPS Receive Process Stopped, receive state = stop 0 RO/LH* 7 RDU Receive Descriptor Unavailable 1: while the next receive descriptor can’t be applied by AN983B. The receive process is suspended in this situation. To restart the receive process, the ownership bit of next receive descriptor should be set to AN983B and a receive poll demand command should be issued (or a new recognized frame is received, if the receive poll demand is not issued). 0 RO/LH* 6 RCI Receive Completed Interrupt 1: while a frame reception is completed. 0 RO/LH* 5 TUF Transmit Under-Flow 1: while the transmit FIFO had an under-flow condition happened during transmitting. The transmit process will enter the suspended state and report the under-flow error on bit1 of TDES0. 0 RO/LH* 4 --- Reserved 3 TJT Transmit Jabber Timer Time-out 1: while the transmit jabber timer expired. The transmit processor will enter the stop state and the transmit jabber time-out flag of bit 14 of TDES0 will be asserted. 0 RO/LH* 2 TDU Transmit Descriptor Unavailable 1: while the next transmit descriptor can’t be applied by AN983B. The transmission process is suspended in this situation. To restart the transmission process, the ownership bit of next transmit descriptor should be set to AN983B and if the transmit automatic polling is not enabled then a transmit poll demand command should be issued. 0 RO/LH* 1 TPS Transmit Process Stopped. 1: while transmit state = stop 0 RO/LH* 0 TCI Transmit Completed Interrupt. 1: means a frame transmission is completed while bit 31 of TDES1 is asserted in the first transmit descriptor of the frame. 0 RO/LH* LH = High Latching and cleared by writing 1. CSR6 (offset = 30h), NAR - Network access register Bit # Name Descriptions Default Val RW Type ADMtek Inc. www.admtek.com.tw Rev. 1.8 32 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |