AN983 datasheet(42/91 Pages) ETC

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AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

0: de-assert pmez signal

RWP

Reset Wake-up Pattern Data Register Pointer

0: Normal

1: Reset

R/W

PAUSE

PAUSE function control to disable or enable the PAUSE

function for flow control. The default value of PAUSE is

decided by the result of Auto-Negotiation. Driver can force

to enable or disable it after the Auto-Negotiation completed.

0: PAUSE function is disabled.

1: PAUSE function is enabled

R/W

RTE

Receive Threshold Enable.

1: the receive FIFO threshold is enabled.

0: disable the receive FIFO threshold selection in bit 3~2 of

this register, the receive threshold is set to 64-byte.

R/W

3~2

DRT

Drain Receive Threshold

00: 32 bytes (8 DW)

01: 64 bytes (16 DW)

10: store-and -forward

11: reserved

R/W

SINT

Software interrupt.

R/W

ATUR

1: enable automatically transmit-underrun recovery.

R/W

CSR19 (offset = 8ch) - PCIC, PCI bus performance counter

Bit #

Name

Descriptions

Default Val RW Type

31~16

CLKCNT

The number of PCI clock from read request asserted to

access completed. This PCI clock number is accumulated all

the read command cycles from last CSR19 read to current

CSR19 read.

RO*

15~8

---

Reserved

7~0

DWCNT

The number of double word accessed by the last bus master.

This double word number is accumulated all the bus master

data transactions from last CSR19 read to current CSR19

read.

RO*

RO* = Read only and cleared by reading.

CSR20 (offset = 90h) - PMCSR, Power Management Command and Status

(The same register value mapping to CR49-PMR1.)

Bit #

Name

Descriptions

Default Val RW Type

31~16

---

Reserved

PMES

PME_Status, This bit is set when the AN983B would normally

assert the PME# signal for wakeup event, this bit is

independent of the state of the PME-En bit.

Writing a “1” to this bit will clear it and cause the AN983B to

stop asserting a PME#(if enabled). Writing a “0” has no

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

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