AN983 datasheet(2/91 Pages) ETC

2 / 91 page

AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

Datasheet Revision History

Revision Date

Revision

Description

Oct, 2000

0.1

Draft data sheet for review

Feb, 2001

1.0

First release

Mar, 2001

1.1

Add CSR15.bit28 MRXCK

Add CSR18.bit26 PMEP

Add CSR18.bit27 PMEPEN

Sep, 2001

1.2

Add 25MHz crystal accuracy

Revise PHY registers

Sep, 2001

1.3

Revise product logo of Pin assignment diagram

Sep, 2001

1.4

P.17 MrxD0~D3

P.23 CIOSA : 1 means enable ; 0 means disable

P.14 Add LED info to pin diagram

JULY, 2002

1.5

P.25 Offset 80h, DID default value : 0981h

P.40 CSR18[25] / PWRS_clr : 1 means PCI_reset rising will clear

CR49[1:0]/PWRS

JULY, 2002

1.6

P.85 FIG21, FIG22, FIG23, FIG24 added for MII interface signal

timing.

JULY, 2002

1.7

P.45 Unicast registers added

MAY, 2003

1.8

P.69 Modify some error statement about Loop-back Operation of

transceiver

T able- 1

Revision History

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

AN983 数据表(PDF) 2 Page - List of Unclassifed Manufacturers

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