AN983 datasheet(52/91 Pages) ETC

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AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

The AN983B provides receive and transmit descriptors for packet buffering and management.

7.4.1 RECEIVE DESCRIPTOR

7.4.1.1 Receive Descriptor Table

RDES0

Own

Status

RDES1

---

Control

Buffer2 byte-count

Buffer1 byte-count

RDES2

Buffer1 address (DW boundary)

RDES3

Buffer2 address (DW boundary)

Descriptors and receive buffers addresses must be longword alignment

7.4.1.2 Receive Descriptor Descriptions

RDES0

Bit #

Name

Descriptions

OWN

Own bit

1: indicate the new receiving data can be put into this descriptor

0: Host does not move the receiving data out yet.

30-16

Frame length, including CRC. This field is valid only in last descriptor

Error summary, OR of the following bit

0: overflow

1: CRC error

6: late collision

7: frame too long

11: runt packet

14: descriptor error

This field is valid only in last descriptor.

Descriptor error. This bit is valid only in last descriptor

1: the current receiving packet is not able to put into the current valid descriptor.

This packet is truncated.

13-12

Data type.

00: normal

01: MAC loop-back

10: Transceiver loop-back

11: remote loop-back

These bits are valid only in last descriptor

Runt frame (packet length < 64 bytes). This bit is valid only in last descriptor

Multicast frame. This bit is valid only in last descriptor

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

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