AN983 datasheet(62/91 Pages) ETC

62 / 91 page

AN983B

PCI/miPCI Fast Ethernet Controller with integrated PHY

place the 1st packet data into host memory

issue transmit demand

FIFO-to-host memory operation (1st packet)

time

Transmit enable

place the 2nd packet data into host memory

check the next

packet

check point

FIFO-to-host memory operation (2nd packet)

transmit threshold

place the 3rd packet data into host memory

1st packet is

transmitted, check

the 3rd packet

FIFO-to-host memory operation (3rd packet)

IFG

check point

1st packet

2nd packet

handled by driver

handled by AN983B

Fig -

Transmit data flow of pre-fetch data

8.3.3 TRANSMIT EARLY INTERRUPT SCHEME

handled by driver

handled by AN983B

Host to TX-FIFO Memory

Operation

Transmit data from FIFO to Media

Normal Interrupt after Transmit

Completed

Driver return buffer to upper layer

Early Interrupt after Host to TX-

FIFO Operation Completed

Driver return buffer to upper layer

The saved time when transmit

early interrupt is implemented

time

Fig -

Transmit normal interrupt and early interrupt comparison

ADMtek Inc.

www.admtek.com.tw

Rev. 1.8

AN983 数据表(PDF) 62 Page - List of Unclassifed Manufacturers

AN983 数据表(HTML) 62 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

数据表下载