数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

AN983 数据表(PDF) 41 Page - List of Unclassifed Manufacturers

部件名 AN983
功能描述  PCI/miniPCI-to-Ethernet LAN Controller
PDF  91 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

AN983 数据表(HTML) 41 Page - List of Unclassifed Manufacturers

Back Button AN983 Datasheet HTML 37Page - List of Unclassifed Manufacturers AN983 Datasheet HTML 38Page - List of Unclassifed Manufacturers AN983 Datasheet HTML 39Page - List of Unclassifed Manufacturers AN983 Datasheet HTML 40Page - List of Unclassifed Manufacturers AN983 Datasheet HTML 41Page - List of Unclassifed Manufacturers AN983 Datasheet HTML 42Page - List of Unclassifed Manufacturers AN983 Datasheet HTML 43Page - List of Unclassifed Manufacturers AN983 Datasheet HTML 44Page - List of Unclassifed Manufacturers AN983 Datasheet HTML 45Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 41 / 91 page
background image
AN983B
PCI/miPCI Fast Ethernet Controller with integrated PHY
25
PWRS_clr 1: PCI_reset rising will automatically reset CR49/ PWRS[1:0]
to 00h.
0 from
EERROM
R/W
24
Pmes_stic
ky
1: pmez sticky: While pmez signal is asserted by wake up
event, it cannot be auto de-asserted. The software should
clear CR49<15> PMES bit to de-assert the pmez signal.
0: pmez auto de-asserted: While pmez signal is asserted by
wake up event, it will be de-asserted by power up
automatically.
0
From EEPROM
R/W
23
4_3LED
If this bit is reset, 3 LED mode is selected, the LEDs
definition is:
100/10 speed
Link/Activity
Full Duplex/Collision
If this bit is set, 4 LED mode is selected, the LEDs definition
is:
100 Link
10 Link
Activity
Full Duplex/Collision
0
From EEPROM
R/W
22, 21
RFS
Receive FIFO size control
11: 1K
10: 2K
01,00: reserved
10
From
EEPROM
R/W
20
CRD
Clock Run (clk-run pin) disable
1: disables the function of clock run supports to PCI.
0
From EEPROM
R/W
19
PM
Power Management, enables the AN983B whether to activate
the Power Management abilities. When this bit is set into “0”
the AN983B will set the Cap_Ptr register to zero, indicating
no PCI compliant power management capabilities.
The value of this bit will be mapped to NC-bit 20 of CR1.
In PCI Power Management mode, the Wake-up events include
“Wake-up Frame Received”, “Magic Packet Received” and
“Link Status Changed” depends on the CSR13 settings
1
From EEPROM
RO
18
APM
APM mode, this bit is effective when PM (csr18 [19]) =1
1: Magic Packet wake-up event default enable
0: Magic Packet wake-up event default disable
1
From EEPROM
R/W
17
LWS
Should be 0
0
From EEPROM
R/W
16~8
----
Reserved
7
D3_APM
D3_cold APM_mode_en for PC99 certification
It doesn’t matter the status of PEM_EN, the pmez signal can
be asserted by programming this bit
1: Assert pmez signal
0
R/W
ADMtek Inc.
www.admtek.com.tw
Rev. 1.8
41



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com