TNETV2840ENGGU datasheet(18/91 Pages) TI1

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Introduction

December 1999 − Revised October 2008

SPRS122F

Table 2−3. Signal Descriptions (Continued)

NAME

DESCRIPTION

TYPE†

HOST-PORT INTERFACE SIGNALS (CONTINUED)

HMODE¶

HPI mode select. When this pin is low, it selects the HPI multiplexed address/data mode. The multiplexed address/data

mode allows hosts with multiplexed address/data lines access to the HPI registers HPIA, HPIC, and HPID.

Host-to-DSP and DSP-to-host interrupts are supported in this mode.

When HMODE is high, it selects the HPI nonmultiplexed mode. HPI nonmultiplexed mode allows hosts with separate

address/data buses to access the HPI address range by way of the 19-bit address bus and the HPI data (HPID) register

via the 16-bit data bus. Host-to-DSP and DSP-to-host interrupts are not supported in this mode.

HAS¶#

HPI address latch enable (ALE) or address strobe input. Hosts with multiplexed address and data pins require HAS

to latch the address in the HPIA register. This signal is used only in HPI multiplexed address/data mode

(HMODE = 0).

HRDY

O/Z§

HPI data ready output. The ready output informs the host when the HPI is ready for the next transfer. While driving,

it is in output state and while not driving, it is in high-Z state.

HR/W

HPI read/write strobe. This signal is used by the host to control the direction of an HPI transfer.

HDS1¶#

¶#

HPI data strobes. Driven by the host read and write strobes to control HPI transfers.

HDS1¶#

HDS2¶#

HPI data strobes. Driven by the host read and write strobes to control HPI transfers.

HCS¶#

HPI chip select. Must be active during HPI transfers and can remain active between concurrent transfers.

PRIMARY

D_HINT

C_HINT

B_HINT

A_HINT

O/Z§

HA5

HA4

HA3

HA2

Host interrupt pins. HPI can interrupt the host by asserting this low. The host can clear this

interrupt by writing a “1” to the HINT bit of the HPIC register. Only supported in HPI

multiplexed address/data mode (HMODE pin low)

HCNTL1

HCNTL0

HA1

HA0

HPI control pins. These pins select a host access to the HPIA, HPIC, and HPID registers.

Only supported in HPI multiplexed address/data mode (HMODE pin low)

HPI_SEL1

Subsystem HPI module select

HPI_SEL1

HPI_SEL2

Subsystem HPI module select

MULTICHANNEL BUFFERED SERIAL PORTS 0, 1, AND 2 SIGNALS

A_BCLKR0#

B_BCLKR0#

C_BCLKR0#

D_BCLKR0#

I/O/Z§

Receive clocks. x_BCLKR0 serve as the serial shift clocks for the buffered serial-port receiver. Input from an external

clock source for clocking data into the McBSP. When not being used as clocks, these pins can be used as

general-purpose I/Os by setting RIOEN = 1.

x_BCLKR0 can be configured as outputs by way of the CLKRM bit in the PCR register.

A_BCLKX0#

B_BCLKX0#

C_BCLKX0#

D_BCLKX0#

I/O/Z§

Transmit clocks. Clock signals used to clock data from the transmit register. These pins can also be configured as

inputs by setting CLKXM = 0 in the PCR register. x_BCLKX0 can be sampled as inputs by way of the IN1 bit in the

SPC register. When not being used as clocks, these pins can be used as general-purpose I/Os by setting XIOEN = 1.

A_BDR0

B_BDR0

C_BDR0

D_BDR0

Buffered serial data receive (input) pins. When not being used as data-receive pins, these pins can be used as

general-purpose I/Os by setting RIOEN = 1.

† I = Input, O = Output, S = Supply, Z = High Impedance

‡ This pin has an internal bus holder controlled by way of the BSCR register in TMS320C54x cLEAD core of DSP subsystem A.

§ This pin is placed in high-impedance when the EMU1/OFF pin operates as OFF and when EMU1/OFF = 0, this case is exclusively for testing

and emulation purposes.

¶ This pin has an internal pullup resistor.

# These pins are Schmitt triggered inputs.

|| This pin is used by Texas Instruments for device testing and should be left unconnected.

kThis pin has an internal pulldown resistor.

hAlthough this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,

a buffer is recommended to ensure the VIL and VIH specifications are met.

NOTE: Pins highlighted in grey indicate the multiplexed function of the pin.

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