TNETV2840ENGGU datasheet(48/91 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS122F

WDFLAG

WDEN

Reserved

PREMD

WDKEY

R/W+0

R/W+1

R/W+0

LEGEND: R = Read, W = Write, +0 = Value at reset

Figure 3−24. Watchdog Timer Second Control Register (WDTSCR)

Table 3−13. WDTSCR Bit Description

BIT

NO.

BIT

NAME

FUNCTION

WDFLAG

Watchdog flag bit. This bit can be cleared by enabling the watchdog timer, by device global reset, and by being

written with “1”.

It is set by a watchdog time-out.

0 =

No watchdog time-out occurred

1 =

Watchdog time-out occurred

WDEN

Watchdog timer enable bit.

0 =

Watchdog disable. Default value after device reset. Watchdog output pin is disconnected to the

watchdog time-out event, counter starts to run.

1 =

Watchdog enable. Once enabled, the watchdog output pin is connected to the watchdog time-out

event, and can be disabled by watchdog time-out or reset.

Reserved

PREMD

Prescalar mode select bit.

0 =

Direct mode, TDDR is 4-bit reload prescalar.

1 =

Indirect mode, TDDR is used to select individual prescalar value (default value after local or global

hardware reset).

11−0

WDKEY

12-bit watchdog reset key, only the sequence of a 5C6h followed by an A7Eh services the watchdog.

The watchdog has to be serviced periodically with the sequence of 5C6h followed by A7Eh, written to WDKEY

before the watchdog timer times out. Both 5C6h and A7Eh are allowed to be written to WDKEY. Only the

sequence of 5C6h followed by A7Eh, to WDKEY services the watchdog. Any other writes to WDKEY will

trigger the watchdog time-out immediately, and consequently:

•

the watchdog output pin will generate an active-low pulse (6H ns, H=0.5 clock cycle)

•

the WDFLAG bit in WDTSCR will be set to 1

•

the internal maskable WD interrupt (WD_TINT) will be triggered

Read from WDTSCR register will not cause time-out.

When the watchdog is in time-out state, the watchdog is disabled and WDEN is cleared. The watchdog output

pin (x_WTOUT) is disconnected to the watchdog time-out event. Finally, the timer is reloaded and continues

to run.

Out of reset, the watchdog is disabled, and reads and writes to the watchdog registers are allowed. Once 5C6h

is written to WDKEY in the WDTSCR register from the initial state, the watchdog enters the preactive state.

The next write to the WDTSCR register should be completed with a “1” written to WDEN and A7Eh written

to WDKEY. This causes the watchdog timer to enter the active state. Once the watchdog is enabled, it cannot

be disabled by software. Any writes to the WDTSCR register from the active or service states that do not write

5C6h or A7Eh to WDKEY will result in an immediate watchdog time-out. Writing the sequence of 5C6h and

A7Eh to WDKEY causes the watchdog timer to transition between the active and service states. The transition

from the service state to the active state results in the timer register reload that is necessary to keep the

watchdog timer from timing out. Each time the watchdog is serviced by the sequence, the watchdog timer

counter and prescalar will automatically be reloaded.

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