TNETV2840ENGGU datasheet(69/91 Pages) TI1

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Electrical Specifications

December 1999 − Revised October 2008

SPRS122F

5.6

Reset, x_BIO, and Interrupt Timings

Table 5−5 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5−4 and

Figure 5−5).

Table 5−5. Reset, x_BIO, and Interrupt Timing Requirements

MIN

MAX

UNIT

th(RS)

Hold time, x_RS after CLKOUT low

th(BIO)

Hold time, x_BIO after CLKOUT low

th(INT)

Hold time, x_INT, x_NMI, after CLKOUT low†

tw(RSL)

Pulse duration, x_RS low‡§

4H+4

tw(BIO)

Pulse duration, x_BIO low, synchronous†

tw(INTH)

Pulse duration, x_INT, x_NMI high (synchronous)†

tw(INTL)

Pulse duration, x_INT, x_NMI low (synchronous)†

tw(INTL)WKP Pulse duration, x_INT, x_NMI low for IDLE2/IDLE3 wakeup†

tsu(RS)

Setup time, x_RS before CLKIN low§

tsu(BIO)

Setup time, x_BIO before CLKOUT low

tsu(INT)

Setup time, x_INT, x_NMI, x_RS before CLKOUT low

† The external interrupts (x_INT, x_NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer, which samples these inputs with

consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is corresponding

to a three-CLKOUT sampling sequence.

‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, x_RS must be held low for at least 50 µs to ensure

synchronization and lock-in of the PLL.

§ x_RS can cause a change in clock frequency, changing the value of H (see Section 3.2.6).

x_BIO

CLKOUT

x_RS, x_NMI, x_INT

CLKIN

th(BIO)

th(RS)

tsu(INT)

tw(BIO)

tsu(BIO)

tw(RSL)

tsu(RS)

Figure 5−4. Reset and x_BIO Timings

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