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TNETV2840ENGGU 数据表(PDF) 56 Page - Texas Instruments |
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TNETV2840ENGGU 数据表(HTML) 56 Page - Texas Instruments |
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56 / 91 page  Functional Overview 56 December 1999 − Revised October 2008 SPRS122F Table 3−23. Peripheral Memory-Mapped Registers for Each DSP Subsystem NAME ADDRESS (HEX) DESCRIPTION DRR20 20 McBSP 0 Data Receive Register 2 DRR10 21 McBSP 0 Data Receive Register 1 DXR20 22 McBSP 0 Data Transmit Register 2 DXR10 23 McBSP 0 Data Transmit Register 1 TIM 24 Timer Register PRD 25 Timer Period Register TCR 26 Timer Control Register TSCR 27 Timer Second Control Register − 28 Reserved BSCR 29 Bank-Switching Control Register — 2A−2B Reserved HPIC 2C HPI Control Register (HMODE=0 only) — 2D−2F Reserved DRR22 30 McBSP 2 Data Receive Register 2 DRR12 31 McBSP 2 Data Receive Register 1 DXR22 32 McBSP 2 Data Transmit Register 2 DXR12 33 McBSP 2 Data Transmit Register 1 SPSA2 34 McBSP 2 Subbank Address Register† SPSD2 35 McBSP 2 Subbank Data Register† — 36−37 Reserved SPSA0 38 McBSP 0 Subbank Address Register† SPSD0 39 McBSP 0 Subbank Data Register† — 3A−3B Reserved GPIO 3C General-Purpose I/O Register — 3D Reserved CSIDR 3E Chip Subsystem ID register — 3F Reserved DRR21 40 McBSP 1 Data Receive Register 2 DRR11 41 McBSP 1 Data Receive Register 1 DXR21 42 McBSP 1 Data Transmit Register 2 DXR11 43 McBSP 1 Data Transmit Register 1 — 44−47 Reserved SPSA1 48 McBSP 1 Subbank Address Register† SPSD1 49 McBSP 1 Subbank Data Register† — 4A−4B Reserved TIM 4C Watchdog Timer Register PRD 4D Watchdog Timer Period Register TCR 4E Watchdog Timer Control Register WDTSCR 4F Watchdog Timer Second Control Register DMMR 50 Data Memory Map Register — 51−53 Reserved DMPREC 54 DMA Priority and Enable Control Register DMSA 55 DMA Subbank Address Register‡ DMSDI 56 DMA Subbank Data Register with Autoincrement‡ †See Table 3−24 for a detailed description of the McBSP control registers and their subaddresses. ‡See Table 3−25 for a detailed description of the DMA subbank addressed registers. |
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