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TNETV2840ENGGU 数据表(PDF) 27 Page - Texas Instruments |
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TNETV2840ENGGU 数据表(HTML) 27 Page - Texas Instruments |
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27 / 91 page  Functional Overview 27 December 1999 − Revised October 2008 SPRS122F Page 0 Data Memory Page 1 Program Memory Page 2 Page 3 0000h 8000h FFFFh MPDD MPDD Page 0 Data Memory Page 1 Program Memory Page 2 Page 3 MPCD3 0000h 8000h FFFFh MPDD reserved MPCD3 MPCD0 MPCD1 MPCD2 MPCD0 MPCD1 MPCD2 MPDD MPDD MPDD MPCD3 MPCD3 MPCD3 Memory Map with OVLY = 1 Memory Map with OVLY = 0 MDD0 or MDD1 MDD0 or MDD1 NOTES: A. MPDD: local program/data memory in subsystem D B. MDD: local data memory in subsystem D. MDD is controlled by the data memory map register (DMMR). DMMR=0, MDD0 is mapped in 8000h − FFFFh. DMMR=1, MDD1 is mapped in 8000h − FFFFh. C. MPCD: shared program memory in subsystems C and D Figure 3−6. Subsystem D CPU Memory Map Figure 3−7 shows the CPU data memory map. The lower 32K-word data memory location in all pages is the overlay area. Program memory has overlay area over the lower 32K words on all pages as well. The overlay areas refer to: 1. When OVLY = 1, the lower 32K words of data space are mapped to the lower 32K words of all program pages in the memory map. 2. When OVLY = 0, the lower 32K words of data space are mapped only to the lower 32K words of data space and the lower 32K words of program page 3 are mapped to the lower 32K words of all program pages. |
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