TNETV2840ENGGU datasheet(11/91 Pages) TI1

11 / 91 page

Features

December 1999 − Revised October 2008

SPRS122F

TMS320VC5441 Features

D 532-MIPS Quad-Core DSP Consisting of

Four Independent Subsystems

D Each Core has an Advanced Multibus

Architecture With Three Separate 16-Bit

Data Memory Buses and One Program Bus

D 40-Bit Arithmetic Logic Unit (ALU)

Including a 40-Bit Barrel-Shifter and Two

40-Bit Accumulators Per Core

D Each Core has a 17-Bit × 17-Bit Parallel

Multiplier Coupled to a 40-Bit Adder for

Non-Pipelined Single-Cycle Multiply/

Accumulate (MAC) Operations

D Each Core has a Compare, Select, and

Store Unit (CSSU) for the Add/Compare

Selection of the Viterbi Operator

D Each Core has an Exponent Encoder to

Compute an Exponent Value of a 40-Bit

Accumulator Value in a Single Cycle

D Each Core has Two Address Generators

With Eight Auxiliary Registers and Two

Auxiliary Register Arithmetic Units

(ARAUs)

D Total 640K-Word × 16-Bit Dual-Access

On-Chip RAM (256K-Word x 16-Bit Shared

Memory and 96K-Word x 16-Bit Local

Memory Per Subsystem)

D Single-Instruction Repeat and

Block-Repeat Operations

D Instructions With 32-Bit Long Word

Operands

D Instructions With 2 or 3 Operand Reads

D Fast Return From Interrupts

D Arithmetic Instructions With Parallel Store

and Parallel Load

D Conditional Store Instructions

D Output Control of CLKOUT

D Output Control of Timer Output (TOUT)

D Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions

D Dual 1.6-V (Core) and 3.3-V (I/O) Power

Supplies for Low-Power, Fast Operations

D 7.5-ns Single-Cycle Fixed-Point Instruction

D Twenty-Four Channels of Direct Memory

Access (DMA) for Data Transfers With No

CPU Loading (Six Channels Per

Subsystem)

D Twelve Multichannel Buffered Serial Ports

(McBSPs), Each With 128-Channel

Selection Capability (Three McBSPs per

Subsystem)

D 16-Bit Host-Port Interface (HPI)

D Software-Programmable Phase-Locked

Loop (PLL) Provides Several Clocking

Options (Requires External TTL Oscillator)

D On-Chip Scan-Based Emulation Logic,

IEEE Standard 1149.1{ (JTAG) Boundary-

Scan Logic

D Four Software-Programmable Timers

(One Per Subsystem)

D Four Software-Programmable Watchdog

Timers (One Per Subsystem)

D Sixteen General-Purpose I/Os

(Four Per Subsystem)

D Provided in 176-pin Plastic Low-Profile

Quad Flatpack (LQFP) Package

(PGF Suffix)

D Provided in 169-ball MicroStar BGAt

Package (GGU Suffix)

MicroStar BGA is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

† IEEE Standard 1149.1-1990, Standard Test-Access Port and Boundary Scan Architecture.

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