TNETV2840ENGGU datasheet(47/91 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS122F

Table 3−12. WDTCR Bit Description

BIT

NO.

BIT

NAME

FUNCTION

15−12

Reserved

SOFT

Used in conjunction with the FREE bit to determine the state of the timer when a breakpoint is encountered in

the HLL debugger.

When FREE = 0 and SOFT = 0 the timer stops immediately.

When FREE = 0 and SOFT = 1, the timer stops when the counter decrements to 0.

FREE

Used in conjunction with the SOFT bit to determine the state of the timer when a breakpoint is encountered in

the HLL debugger.

When FREE = 0, the SOFT bit selects the timer mode.

When FREE = 1, the timer runs free regardless of the SOFT bit.

9−6

PSC

Timer prescalar counter, used only when PREMD = 0 (in WDTSCR register) and the prescaler is in direct mode.

5−4

Reserved

3−0

TDDR

Timer prescalar.

Case 1: When PREMD = 0, TDDR is a 4-bit reload prescalar. When PSC decrements to 0, PSC is loaded with

the contents of TDDR.

Case 2: When PREMD = 1,TDDR is an indirect prescalar, the contents in TDDR is used to specify the timer

prescalar.

TDDR[3:0]

PRESCALAR

0000

0001h

0001

0003h

0010

0007h

0011

000Fh

0100

001Fh

0101

003Fh

0110

007Fh

0111

00FFh

1000

01FFh

1001

03FFh

1010

07FFh

1011

0FFFh

1100

1FFFh

1101

3FFFh

1110

7FFFh

1111

FFFFh (Default)

3.2.5.5

WDTSCR Register

This 16-bit register contains bits to indicate watchdog flag, to enable watchdog, to set prescalar mode as well

as to provide the 12-bit WDKEY for watchdog service.

WDTSCR bit fields are shown in Figure 3−24 and are described in Table 3−13.

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