TNETV2840ENGGU datasheet(28/91 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS122F

Memory-

Mapped

Registers

00 0000

00 005F

00 0060

00 7FFF

00 8000

00 FFFF

Hex

Data Memory

16K Words

00 3FFF

00 4000

00 BFFF

00 C000

DARAM0

DARAM1

DARAM2

(DMMR=0)

DARAM4

DARAM3

DARAM5

(DMMR=0)

(DMMR=1)

NOTE: The upper part of data memory is controlled by the Data Memory Map Register (DMMR).

1. DMMR=0, DARAM2 and DARAM3 are mapped in 8000h − FFFFh.

2. DMMR=1, DARAM4 and DARAM5 are mapped in 8000h − FFFFh.

Figure 3−7. Detailed Memory Map of Local Data Memory Relative to CPU Subsystems A, B, C, and D

3.1.2 On-Chip Dual-Access RAM (DARAM)

Each 5441 subsystem has 96K 16-bit words of on-chip DARAM (six blocks of 16K words). Each of these

DARAM blocks can be accessed twice per machine cycle. This memory is intended primarily to store data

values; however, it can be used to store program as well. At reset, the DARAM is mapped into data memory

space (OVLY=0). The lower part of DARAM (0000h−8000h) can be mapped into program/data memory space

by setting the OVLY bit in the processor-mode status (PMST) register of the TMS320C54x

 cLEAD CPU in

each DSP subsystem.

3.1.3 On-Chip Two-Way Shared RAM

There are 128K 16-bit words of on-chip RAM (four blocks of 32K words) that are shared between subsystems

A and B. There are 128K 16-bit words of on-chip RAM (four blocks of 32K words) that are shared between

subsystems C and D. This memory is intended to store program only. Both subsystems are able to make one

instruction fetch from any location in the two-way shared memory each cycle simultaneously. No subsystem

CPU can write to the shared memory as only the DMA can write to shared memory.

If any of the CPU program fetches are requested at the same time as an M-bus transfer request, the CPU is

stalled until all M bus transfers are completed. In other words, any read or write requested by the M bus (driven

by DMA controller or HPI) has priority over the CPUs’ (A, B, C, and D) program fetches. The M-bus reads or

writes always take two cycles to complete.

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