TNETV2840ENGGU datasheet(40/91 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS122F

The selection of the sample rate generator (SRG) clock input source is made by the combination of the CLKSM

and SCLKME bit values as shown in Table 3−7.

Table 3−7. Sample Rate Generator Clock Source Selection

SCLKME

CLKSM

SRG Clock Source

Reserved

CPU clock

BCLKRn pin

BCLKXn pin

When either of the bidirectional pins, BCLKRn or BCLKXn, is configured as the clock input, its output buffer

is automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKRn pin is configured as

the SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG output

by setting PCR[9:8] for CLKXM = 1 and CLKRM = 1. However, the SRG output is only driven onto the BCLKXn

pin because the BCLKR output is automatically disabled.

3.2.3.2

Multichannel Selection

The McBSP supports independent selection of multiple channels for the transmitter and receiver. When

multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using

time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save

memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for

transmission and reception. Up to a maximum of 128 channels in a bit stream can be enabled or disabled.

The 5441 McBSPs have two working modes that are selected by setting the RMCME and XMCME bits in the

multichannel control registers MCR1x and MCR2x, respectively (see Figure 3−16 and Figure 3−17). For a

description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals

(literature number SPRU302).

•

In the first mode, when RMCME = 0 and XMCME = 0, there are two partitions (A and B), with each

containing 16 channels as shown in Figure 3−16 and Figure 3−17. This is compatible with the McBSPs

used in the 5420, where only 32-channel selection is enabled (default).

Reserved

XMC

XPBBLK

XPABLK

XCBLK

XMCM

R,+0

RW,+0

R,+0

RW,+0

LEGEND: R = Read, W = Write, +0 = Value at reset; x = McBSP 0,1, or 2

Figure 3−16. Multichannel Control Register 2 for McBSPx (MCR2x)

Reserved

RMC

RPBBLK

RPABLK

RCBLK

RMCM

R,+0

RW,+0

R,+0

RW,+0

LEGEND: R = Read, W = Write, +0 = Value at reset; x = McBSP 0,1, or 2

Figure 3−17. Multichannel Control Register 1 for McBSPx (MCR1x)

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