TNETV2840ENGGU datasheet(30/91 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS122F

3.1.9 Multicore Reset Signals

The 5441 device includes five reset signals: A_RS, B_RS, C_RS, D_RS, and RESET. The A_RS, B_RS,

C_RS, and D_RS local reset signals function as the CPU reset signal for subsystem A, B, C, and D,

respectively. The RESET services as a global reset for the whole device.

The global reset (RESET) is a superset of local resets A_RS, B_RS, C_RS, and D_RS. The assertion of

RESET triggers all the local resets; however, none of the local resets triggers the global reset. The local reset

signals reset the state of the CPU registers and CPU memory-mapped peripheral registers, and upon release,

initiate the reset function. The global reset, RESET, resets the on-chip PLL and clears the watchdog timer flag

(WDFLAG) bit. The local reset signals are not able to reset the PLL or clear the WDFLAG.

The global reset (RESET) and local resets (x_RS) clears the program counter extension register (XPC) to zero

while the RESET instruction does not affect the XPC.

3.1.10

Device Bootload

The 5441 device supports an HPI boot sequence, which is used to download code while the DSP is in reset.

The external master holds the device in reset while it loads code to the on-chip memory of each subsystem,

subsystem selection is made by HPI_SEL1 and HPI_SEL2 signals. The host can release the 5441 from reset

by using either of the following methods.

•

If the x_RS (x = A, B, C, or D for subsystem A, B, C, or D, respectively) pins are held low while RESET

transitions from low to high, the reset of each subsystem will be controlled by the x_RS pins. When the

host has finished downloading code, it can drive x_RS high to release the cores from reset.

•

If the x_RS pins are held high while RESET transitions from low to high, the subsystems will stay in reset

until an HPI data write to address 0x2F occurs. This means the host can download code to subsystem

x and then release core x from reset by writing any data to core x’s address 0x2F via the HPI. The host

can then repeat the sequence for other cores. This mode allows the host to control 5441 reset without

additional hardware.

3.2

On-Chip Peripherals

All the C54x

 devices have the same CPU structure; however, they have different on-chip peripherals

connected to their CPUs. The on-chip peripheral options provided are:

•

DMA controller

•

16-bit host-port interface I/O ports

•

Multichannel buffered serial ports (McBSPs)

•

A hardware timer

•

A hardware watchdog timer

•

A software-programmable clock generator using a phase-locked loop (PLL)

•

General-purpose I/O

3.2.1 Direct Memory Access (DMA) Controller

The 5441 includes four 6-channel direct memory access (DMA) controllers for performing data transfers

independent of the CPU, one controller for each subsystem. The primary function of the 5441 DMA controller

is to provide code overlays and to manage data transfers between on-chip memory, the peripherals, and

off-chip host.

In the background of CPU operation, the 5441 DMA allows movement of data between internal program/data

memory and internal peripherals, such as the McBSPs and the HPI. Each subsystem has its own independent

DMA with six programmable channels, which allows for six different contexts for DMA operation. The HPI has

a dedicated auxiliary DMA channel. The remapped areas represent address aliasing for DMA accesses within

each subsystem. Figure 3−8 through Figure 3−11 illustrate the local DMA memory map of each subsystem.

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