TNETV2840ENGGU datasheet(73/91 Pages) TI1

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Electrical Specifications

December 1999 − Revised October 2008

SPRS122F

5.9

Multichannel Buffered Serial Port Timing

5.9.1 McBSP0/1/2 Transmit and Receive Timings

The serial port timings that are referenced to CLKOUT are actually related to the internal CPU clock frequency.

These timings are not affected by the value of the DIVFCT bit field in the BSCR register (see Section 3.2.2.5

of this data manual for details on the BSCR register). Any references to CLKOUT in these timing parameters

refer to the CLKOUT timings when no divide factor is selected (DIVFCT = 00b).

Table 5−9 and Table 5−10 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5−10 and Figure 5−11).

Table 5−9. McBSP0/1/2 T

ransmit and Receive Timing Requirements†

MIN

MAX

UNIT

tc(BCKRX)

Cycle time, x_BCLKR/X

BCLKR/X ext

tw(BCKRX)

Pulse duration, x_BCLKR/X low or x_BCLKR/X high

BCLKR/X ext

th(BCKRL-BFRH)

Hold time, external x_BFSR high after x_BCLKR low

BCLKR ext

7.5

th(BCKRL-BDRV)

Hold time, x_BDR valid after x_BCLKR low

BCLKR ext

7.5

th(BCKXL-BFXH)

Hold time, external x_BFSX high after x_BCLKX low

BCLKX ext

7.5

tsu(BFRH-BCKRL)

Setup time, external x_BFSR high before x_BCLKR low

BCLKR ext

7.5

tsu(BDRV-BCKRL)

Setup time, x_BDR valid before x_BCLKR low

BCLKR ext

7.5

tsu(BFXH-BCKXL)

Setup time, external x_BFSX high before x_BCLKX low

BCLKX ext

7.5

tr(BCKRX)

Rise time, x_BCLKR/X

BCLKR/X ext

tf(BCKRX)

Fall time, x_BCLKR/X

BCLKR/X ext

† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are

also inverted.

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