TNETV2840ENGGU datasheet(34/91 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS122F

Table 3−1. DMA Synchronization Events

DSYN VALUE

DMA SYNCHRONIZATION EVENT

0000b

No synchronization used

0001b

McBSP0 Receive Event

0010b

McBSP0 Transmit Event

0011b

McBSP2 Receive Event

0100b

McBSP2 Transmit Event

0101b

McBSP1 Receive Event

0110b

McBSP1 Transmit Event

0111b − 1111b

Reserved

3.2.1.5

DMA Channel Interrupt Selection

The DMA controller can generate a CPU interrupt for each of the six channels. However, channels 0, 1, 2,

and 3 are multiplexed with other interrupt sources. DMA channels 0 and 1 share an interrupt line with the

receive and transmit portions of McBSP2 (IMR/IFR bits 6 and 7), and DMA channels 2 and 3 share an interrupt

line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11). When the 5441 is reset, the

interrupts from these four DMA channels are deselected. The INTSEL bit field in the DMA channel priority and

enable control (DMPREC) register can be used to select these interrupts, as shown in Table 3−2.

Table 3−2. DMA Channel Interrupt Selection

INTSEL Value

IMR/IFR[6]

IMR/IFR[7]

IMR/IFR[10]

IMR/IFR[11]

00b (reset)

BRINT2

BXINT2

BRINT1

BXINT1

01b

BRINT2

BXINT2

DMAC2

DMAC3

10b

DMAC0

DMAC1

DMAC2

DMAC3

11b

Reserved

3.2.2 16-Bit Bidirectional Host-Port Interface (HPI16)

3.2.2.1

HPI16 Memory Map

The HPI16 is an enhanced 16-bit version of the C54x

 DSP 8-bit host-port interface (HPI). The HPI16 is

designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master of the

interface. Each HPI subsystem memory map is identical to its corresponding DMA memory map except the

HPI memory map does not support accesses to any memory-mapped registers.

Some of the features of the HPI16 include:

•

A 16-bit bidirectional data bus

•

Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts

•

Multiplexed and nonmultiplexed address/data modes

•

A 19-bit address bus used in nonmultiplexed mode to allow access to all on-chip (including extended

address pages) memory

•

A 19-bit address register used in multiplexed mode. Includes address autoincrement feature for faster

accesses to sequential addresses

•

Interface to on-chip DMA module to allow access to entire on-chip memory space

•

HRDY signal to hold off host accesses due to DMA latency

•

Control register available in multiplexed mode only. Accessible by either host or DSP to provide host/DSP

interrupts, extended addressing, and data prefetch capability

•

HPI_SEL1 and HPI_SEL2 pins are used to make selection among the four subsystem HPI modules.

•

Both the HPI data bus and address bus have bus-holder features. The bus holders can be

enabled/disabled by the CPUs.

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