TNETV2840ENGGU datasheet(33/91 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS122F

3.2.1.1

DMA Controller Features

The 5441 DMA has the following features:

•

The DMA operates independently of the CPU.

•

The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.

•

The DMA has higher priority than the CPU.

•

Each channel has independently programmable priority.

•

Each channel’s source and destination address registers include configurable indexing modes. The

address can be held constant, postincremented, postdecremented, or adjusted by a programmable value.

•

Each read or write transfer can be initialized by selected events.

•

The DMA supports single-word (16-bit) and double-word (32-bit) transfers.

•

Each DMA channel has independent reload registers.

•

Each DMA channel has independent extended source/destination data page registers.

•

The DMA does not support I/O memory access.

A 16-bit DMA transfer requires four CPU clock cycles to complete—two cycles for reads and two cycles for

writes. Since the DMA controller shares the DMA bus with the HPI module, the DMA access rate is reduced

when the HPI is active.

3.2.1.2

DMA Reload Registers

Each DMA channel has its own reload registers which are utilized when autoinitialization is enabled for the

current DMA channel. The reload registers include:

•

Source address reload register (DMGSAn)

•

Destination address reload register (DMGDAn)

•

Element count reload register (DMGCRn)

•

Frame count reload register (DMGFRn)

The “n” in the register names refers to DMA channel number: 0, 1, 2, 3, 4, and 5.

In the DMPREC register, bit 14 (IAUTO) is used to enable individual reload register for each channel. If that

bit is not set, the channel 0 reload register will be loaded to all chanels (this is backward compatible).

3.2.1.3

Extended Source/Destination Data Page Registers (DMSRCDPn/DMDSTDPn)

The DMA controller has the ability to perform transfers to and from the extended data memory space. The

DMA extended source data page register and extended destination data page register service this purpose

and only the least significant seven bits are used to designate the extended data memory page. Each of the

DMA channels will have one set of these registers for extended data memory page (other than page 0) access.

Data memory space transfers cannot cross 64K page boundaries. If a data page boundary is crossed during

a transfer, the next transfer will wrap on to the same page.

For detailed information on DMA registers, see TMS320C54x DSP Reference Set, Volume 5: Enhanced

Peripherals (literature number SPRU302).

3.2.1.4

DMA Controller Synchronization Events

The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN

bit field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization

event for a channel. The list of possible events and the DSYN values are shown in Table 3−1.

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