TNETV2840ENGGU datasheet(77/91 Pages) TI1

77 / 91 page

Electrical Specifications

December 1999 − Revised October 2008

SPRS122F

5.10 Host-Port Interface (HPI16) Timing

Table 5−13 and Table 5−14 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5−13 through Figure 5−19). In the following tables, DS refers to the logical OR of HCS, HDS1, and

HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).

Table 5−13. HPI16 Timing Requirements

MIN

MAX

UNIT

tsu(HBV-DSL)

Setup time, HAD valid before DS falling edge†‡

th(DSL-HBV)

Hold time, HAD valid after DS falling edge†‡

tsu(HBV-HSL)

Setup time, HAD valid before HAS falling edge†

th(HSL-HBV)

Hold time, HAD valid after HAS falling edge†

tsu(HAV-DSH)

Setup time, address valid before DS rising edge (nonmultiplexed write)‡

tsu(HAV-DSL)

Setup time, address valid before DS falling edge (nonmultiplexed read)‡

−(4H + 5)

th(DSH-HAV)

Hold time, address valid after DS rising edge (nonmultiplexed mode)‡

tsu(HSL-DSL)

Setup time, HAS low before DS falling edge‡

th(HSL-DSL)

Hold time, HAS low after DS falling edge‡

tw(DSL)

Pulse duration, DS low‡

tw(DSH)

Pulse duration, DS high‡

Nonmultiplexed or multiplexed mode

(no increment) memory accesses (or

Reads

10H + 20

(no increment) memory accesses (or

writes to the FETCH bit) with no DMA

activity.

Writes

10H + 10

Cycle time, DS rising edge to next DS

‡

Nonmultiplexed or multiplexed mode

(no increment) memory accesses (or

Reads

16H + 20

Cycle time, DS rising edge to next DS

rising edge‡

(no increment) memory accesses (or

writes to the FETCH bit) with 16-bit

DMA activity.

Writes

16H + 10

Nonmultiplexed or multiplexed mode

(no increment) memory accesses (or

Reads

24H + 20

(no increment) memory accesses (or

writes to the FETCH bit) with 32-bit

DMA activity.

Writes

24H + 10

tc(DSH-DSH)

Cycle time, DS rising edge to next DS

rising edge‡

Multiplexed

(autoincrement)

memory

accesses (or writes to the FETCH bit) with no

DMA activity.

10H + 10

Cycle time, DS rising edge to next DS

rising edge‡

(In autoincrement mode, WRITE

timings are the same as READ

Multiplexed

(autoincrement)

memory

accesses (or writes to the FETCH bit) with

16-bit DMA activity.

16H + 10

timings are the same as READ

timings.)

Multiplexed

(autoincrement)

memory

accesses (or writes to the FETCH bit) with

32-bit DMA activity.

24H + 10

Cycle time, DS rising edge to next DS rising edge for writes to DSPINT and x_HINT

Cycle time, DS rising edge to next DS rising edge for HPIC reads, HPIC XADD bit

writes, and address register reads and writes

tsu(HDV-DSH)W

Setup time, HD valid before DS rising edge‡

th(DSH-HDV)W

Hold time, HD valid after DS rising edge, write‡

tsu(SELV-DSL)

Setup time, HPI_SEL1/SEL2 valid before DS falling edge‡

th(DSH-SELV)

Hold time, HPI_SEL1/SEL2 valid after DS rising edge‡

† HAD stands for HCNTL0, HCNTL1, and HR/W.

‡ DS refers to either HCS or HDS, whichever is controlling the transfer. Refer to the TMS320C54x DSP Reference Set, Volume 5: Enhanced

Peripherals (literature number SPRU302) for information regarding logical operation of the HPI16. These timings are shown assuming that HDS

is the signal controlling the transfer.

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