TNETV2840ENGGU datasheet(45/91 Pages) TI1

45 / 91 page

Functional Overview

December 1999 − Revised October 2008

SPRS122F

3.2.4.4

TSCR Register

This 16-bit register contains bits to set prescalar mode.

Reserved

PREMD

Reserved

R/W+0

LEGEND: R = Read, W = Write, +0 = Value at reset

Figure 3−22. Timer Second Control Register (TSCR)

Table 3−11. TSCR Bit Description

BIT

NO.

BIT

NAME

FUNCTION

15−13

Reserved

PREMD

Prescalar mode select bit.

0 = direct mode, TDDR is a 4-bit reload prescalar (default value after reset).

1 = indirect mode, TDDR is used to select individual prescalar value.

11−0

Reserved

Out of reset, the TIM and PRD registers are set to a maximum value of FFFFh, the PREMD bit (TSCR[12])

is set to 0, the TDDR field (TCR[3:0]) is cleared to 0, and the timer is started.

3.2.5 Watchdog Timer

Each subsystem contains a watchdog timer. The purpose of the watchdog timer is to prevent the system from

lock in case the software becomes trapped in loops with no controlled exit. The watchdog timer has a

“watchdog output” pin associated with it. This watchdog output pin is shared with the x_GPIO2/x_WTOUT pin;

once the watchdog timer is enabled, this pin is automatically configured as x_WTOUT. The watchdog timer

requires a special service sequence to be executed periodically. Without this periodic servicing, the watchdog

timer counter reaches zero and times out. Consequently, an active-low pulse will be asserted on the “watchdog

output” pin and an internal maskable interrupt will be triggered. The watchdog output (x_WTOUT) pin can be

gluelessly external-connected to the local hardware reset or NMI (nonmaskable interrupt). This allows

maximum flexibility in utilizing the watchdog as required by the particular application.

The watchdog timer is a prescaled 16-bit counter that supports up to a 32-bit dynamic range. Out of reset, the

watchdog is disabled in order to allow as much time as needed for code to be loaded into the 5441 on-chip

memory via the HPI. Prior to being enabled, the watchdog counter will, in fact, still count down from its initial

default value using the default prescalar value. When the counter reaches zero, a watchdog time-out event

will occur in that a WD interrupt (WDTINT) request will be sent to the core, and the WDFLAG will be set.

However, since all maskable interrupts are disabled by default at reset, the WDTINT will not be serviced by

the core. Additionally, the watchdog pin (x_WTOUT) is disconnected from the watchdog time-out event, so

no pulse will be generated on this pin. After this time-out, the counter and prescalar will be reloaded

automatically and the watchdog will continue to count, time out, reload, etc. After code-download, the

watchdog can be enabled to connect the x_WTOUT pin to the time-out event. To enable the watchdog, certain

sequence shall be followed as shown in Figure 3−25.

Once the watchdog is enabled, it cannot be disabled by software. It can be disabled by watchdog time-out,

local hardware reset, or global hardware reset. A special key sequence is provided to prevent the watchdog

from being accidentally serviced while the software is trapped in a dead loop or in some other software failures.

TNETV2840ENGGU 数据表(PDF) 45 Page - Texas Instruments

TNETV2840ENGGU 数据表(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

数据表下载

链接网址

TNETV2840ENGGU 数据表(PDF) 45 Page - Texas Instruments

TNETV2840ENGGU 数据表(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

数据表 下载

链接网址

数据表下载