TNETV2840ENGGU datasheet(29/91 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS122F

3.1.4 Extended Data Memory

The data memory space of each 5441 subsystem addresses 128K 16-bit words. There are two pages of data

memory location with each page consisting of 64K words. The 5441 device uses a data memory map register

(DMMR) to facilitate extended data memory access. The DMMR is a peripheral memory-mapped register. The

contents of the DMMR register, once being written with an extended data number by the DSP CPU, will be

associated with the address decoding for all the data memory CPU accesses.

3.1.5 Extended Program Memory

The 5441 device uses a paged extended memory scheme in program space to allow access to 256K 16-bit

words. This extended program memory (each subsystem) is organized into four pages (0−3), pages 0−3 are

two-way shared memory. Each page is 64K words in length. The program counter extension register (XPC)

defines the program page selection. To implement the extended program memory scheme, the 5441 device

includes the following feature:

•

Two C54x

 instructions allow each subsystem CPU access to the on-chip program memory.

−

READA − Read program memory addressed by accumulator A and store in data memory

−

WRITA − Write data to program memory addressed by accumulator A

(Writes not allowed for CPUs to shared program memory)

3.1.6 Program Memory

The program memory is accessible on multiple pages, depending on the XPC value. Within these pages,

memory is accessible depending on the address range.

•

Access in the lower 32K words of each page is dependent on the state of OVLY.

−

OVLY = 0 − Program memory is accessed from program memory page 3 for all values of XPC.

−

OVLY = 1 − Program memory is accessed from local data/program DARAM for all values of XPC.

•

Access in the upper 32K words of each page is dependent on the state of OVLY.

−

OVLY = 0 − All pages of program memory except page 3 (which is reserved) are accessible for all

values of XPC.

−

OVLY = 1 − All pages of program memory are accessible for all values of XPC.

3.1.7 Data Memory

Accesses on extended data spaces are dependent on the value of the data memory map register (DMMR).

Within the page, memory is accessible depending on the address range.

•

Access in the lower 32K words

−

Data memory is accessed from local data/program DARAM for all values of DMMR.

•

Access in the upper 32K words

−

Which data memory block is accessed depends on the value of DMMR.

−

There are four 16K-word DARAM blocks for the upper addresses (8000h − FFFFh)

DMMR=0:

DARAM2 and DARAM3 are mapped to the upper addresses

DMMR=1:

DARAM4 and DARAM5 are mapped to the upper addresses

3.1.8 I/O Memory

The 5441 does not support I/O memory accesses.

C54x is a trademark of Texas Instruments.

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