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TNETV2840ENGGU 数据表(PDF) 78 Page - Texas Instruments |
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TNETV2840ENGGU 数据表(HTML) 78 Page - Texas Instruments |
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78 / 91 page  Electrical Specifications 78 December 1999 − Revised October 2008 SPRS122F Table 5−14. HPI16 Switching Characteristics PARAMETER MIN MAX UNIT td(DSL-HDD) Delay time, DS low to HD driven† 3 20 ns Case 1a: Memory accesses initiated immediately following a write when DMAC is active in 16-bit mode and tw(DSH) was < 18H 32H+20 − tw(DSH) ns Case 1b: Memory accesses initiated by an autoincrement when DMAC is active in 16-bit mode and tw(DSH) was < 18H 16H+20 − tw(DSH) ns Case 1c: Memory accesses not initiated by an autoincrement (or not immediately following a write) when DMAC is active in 16-bit mode 16H+20 ns Case 1d: Memory accesses initiated by an autoincrement when DMAC is active in 16-bit mode and tw(DSH) was ≥ 18H 20 ns Case 1e: Memory accesses initiated immediately following a write when DMAC is active in 16-bit mode and tw(DSH) was < 26H 48H+20 − tw(DSH) ns Delay time, DS low to HD valid Case 1f: Memory access initiated by an autoincrement when DMAC is active in 32-bit mode and tw(DSH) was < 26H 24H+20 − tw(DSH) td(DSL-HDV1) Delay time, DS low to HD valid for first word of an HPI read Case 1g: Memory access not initiated by an autoincrement (or not immediately following a write) when DMAC is active in 32-bit mode 24H+20 ns an HPI read Case 1h: Memory access initiated by an autoincrement when DMAC is active in 32-bit mode and tw(DSH) was ≥ 26H 20 Case 2a: Memory accesses initiated immediately following a write when DMAC is active in 16-bit mode and tw(DSH) was < 10H 20H+20 − tw(DSH) ns Case 2b: Memory accesses initiated by an autoincrement when DMAC is inactive and tw(DSH) was < 10H 10H+20 − tw(DSH) Case 2c: Memory accesses not initiated by an autoincrement (or not immediately following a write) when DMAC is inactive 10H+20 ns Case 2d: Memory accesses initiated by an autoincrement when DMAC is inactive and tw(DSH) was ≥ 10H 20 ns Case 3: HPIC/HPIA reads 20 td(DSL-HDV2) Multiplexed reads with autoincrement. Prefetch completed. 3 20 ns Delay time, DS Memory accesses (or writes to the FETCH bit) when no DMA is active 10H+5 td(DSH-HYH) Delay time, DS high to HRDY high† (writes and Memory accesses (or writes to the FETCH bit) with one or more 16-bit DMA channels active 16H+5 ns td(DSH-HYH) (writes and autoincrement reads) Memory accesses (or writes to the FETCH bit) with one or more 32-bit DMA channels active 24H+5 reads) Writes to DSPINT and x_HINT‡ 4H + 5 tv(HYH-HDV) Valid time, HD valid after HRDY high 6 ns th(DSH-HDV)R Hold time, HD valid after DS rising edge, read† 0 10 ns td(DSL-HYL) Delay time, DS low to HRDY low† 18 ns td(DSH-HYL) Delay time, DS high to HRDY low† 18 ns td(HSL-HYL) Delay time, HAS low to HRDY low, read 18 ns † DS refers to either HCS or HDS, whichever is controlling the transfer. Refer to the TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302) for information regarding logical operation of the HPI16. These timings are shown assuming that HDS is the signal controlling the transfer. ‡ HRDY does not go low for other register accesses. |
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