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TNETV2840ENGGU 数据表(PDF) 19 Page - Texas Instruments |
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TNETV2840ENGGU 数据表(HTML) 19 Page - Texas Instruments |
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19 / 91 page  Introduction 19 December 1999 − Revised October 2008 SPRS122F Table 2−3. Signal Descriptions (Continued) NAME DESCRIPTION TYPE† MULTICHANNEL BUFFERED SERIAL PORTS 0, 1, AND 2 SIGNALS (CONTINUED) A_BDX0 B_BDX0 C_BDX0 D_BDX0 O/Z§ Buffered serial-port transmit (output) pins. When not being used as data-transmit pins, x_BDX0 can be used as general-purpose I/Os by setting XIOEN = 1. A_BFSR0 B_BFSR0 C_BFSR0 D_BFSR0 I/O/Z§ Frame synchronization pins for buffered serial-port input data. The x_BFSR0 pulse initiates the receive-data process over x_BDR0. When not being used as data-receive synchronization pins, these pins can be used as general-purpose I/Os by setting RIOEN = 1. A_BFSX0 B_BFSX0 C_BFSX0 D_BFSX0 I/O/Z§ Buffered serial-port frame synchronization pins for transmitting data. The x_BFSX0 pulse initiates the transmit-data process over the x_BDX0 pin. If x_RS is asserted when x_BFSX0 is configured as output, then x_BFSX0 is turned into input mode by the reset operation. When not being used as data-transmit synchronization pins, these pins can be used as general-purpose I/Os by setting XIOEN = 1. BCLKR1# Receive clock, multiplexed McBSP1 BCLKX1# I Transmit clock, multiplexed McBSP1 BDR1 I Receive data, multiplexed McBSP1 BDX1 O/Z§ Transmit data, multiplexed McBSP1 BFSR1 I Receive frame sync, multiplexed McBSP1 BFSX1 I Transmit frame sync, multiplexed McBSP1 BCLKR2# Receive clock, multiplexed McBSP2 BCLKX2# I Transmit clock, multiplexed McBSP2 BDR2 I Receive data, multiplexed McBSP2 BDX2 O/Z§ Transmit data, multiplexed McBSP2 BFSR2 I Receive frame sync, multiplexed McBSP2 BFSX2 I Transmit frame sync, multiplexed McBSP2 CLOCKING SIGNALS CLKOUT O/Z§ Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the falling edges of this signal. The CLKOUT pin can be turned off by writing a “1” to the CLKOUT bit of the PMST register. Multiplexed as shown below based on the selection bits in the GPIO register CLKOUT O/Z§ GPIO[7] GPIO[6] A_CLKOUT 0 0 (default) B_CLKOUT|| 01 C_CLKOUT|| 10 D_CLKOUT|| 11 CLKIN# I Input clock to the device. CLKIN connects to a PLL. CLKMD# I Clock mode configuration pin at reset. When CLKMD = 0, bypasses PLL; when CLKMD = 1, CLKINx2 † I = Input, O = Output, S = Supply, Z = High Impedance ‡ This pin has an internal bus holder controlled by way of the BSCR register in TMS320C54x cLEAD core of DSP subsystem A. § This pin is placed in high-impedance when the EMU1/OFF pin operates as OFF and when EMU1/OFF = 0, this case is exclusively for testing and emulation purposes. ¶ This pin has an internal pullup resistor. # These pins are Schmitt triggered inputs. || This pin is used by Texas Instruments for device testing and should be left unconnected. kThis pin has an internal pulldown resistor. hAlthough this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs, a buffer is recommended to ensure the VIL and VIH specifications are met. NOTE: Pins highlighted in grey indicate the multiplexed function of the pin. |
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