TNETV2840ENGGU datasheet(55/91 Pages) TI1

55 / 91 page

Functional Overview

December 1999 − Revised October 2008

SPRS122F

3.3

Memory-Mapped Registers

The 5441 has 27 processor memory-mapped registers, which are mapped in data memory space addresses

0h to 1Fh as shown in Table 3−22. Each device also has a set of memory-mapped registers associated with

the peripherals as shown in Table 3−23.

Table 3−22. Processor Memory-Mapped Registers for Each DSP Subsystem

NAME

ADDRESS

DESCRIPTION

NAME

DEC

HEX

DESCRIPTION

IMR

Interrupt Mask Register

IFR

Interrupt Flag Register

—

2−5

Reserved for testing

ST0

Status Register 0

ST1

Status Register 1

Accumulator A Low Word (15−0)

Accumulator A High Word (31−16)

Accumulator A Guard Bits (39−32)

Accumulator B Low Word (15−0)

Accumulator B High Word (31−16)

Accumulator B Guard Bits (39−32)

TREG

Temporary Register

TRN

Transition Register

AR0

Auxiliary Register 0

AR1

Auxiliary Register 1

AR2

Auxiliary Register 2

AR3

Auxiliary Register 3

AR4

Auxiliary Register 4

AR5

Auxiliary Register 5

AR6

Auxiliary Register 6

AR7

Auxiliary Register 7

Stack Pointer

Circular Buffer Size Register

BRC

Block-Repeat Counter

RSA

Block-Repeat Start Address

REA

Block-Repeat End Address

PMST

Processor Mode Status Register

XPC

Extended Program Counter

—

Reserved

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